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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c0638a4553
- Simplify SHPC existence/permission checks (Bjorn Helgaas) - Remove hotplug sample skeleton driver (Lukas Wunner) - Convert pciehp to threaded IRQ handling (Lukas Wunner) - Improve pciehp tolerance of missed events and initially unstable links (Lukas Wunner) - Clear spurious pciehp events on resume (Lukas Wunner) - Add pciehp runtime PM support, including for Thunderbolt controllers (Lukas Wunner) - Support interrupts from pciehp bridges in D3hot (Lukas Wunner) * pci/hotplug: PCI: pciehp: Deduplicate presence check on probe & resume PCI: pciehp: Avoid implicit fallthroughs in switch statements PCI: Whitelist Thunderbolt ports for runtime D3 PCI: Whitelist native hotplug ports for runtime D3 PCI: sysfs: Resume to D0 on function reset PCI: pciehp: Resume parent to D0 on config space access PCI: pciehp: Resume to D0 on enable/disable PCI: pciehp: Support interrupts sent from D3hot PCI: pciehp: Obey compulsory command delay after resume PCI: pciehp: Clear spurious events earlier on resume PCI: portdrv: Deduplicate PM callback iterator PCI: pciehp: Avoid slot access during reset PCI: pciehp: Always enable occupied slot on probe PCI: pciehp: Become resilient to missed events PCI: pciehp: Tolerate initially unstable link PCI: pciehp: Declare pciehp_enable/disable_slot() static PCI: pciehp: Drop enable/disable lock PCI: pciehp: Enable/disable exclusively from IRQ thread PCI: pciehp: Track enable/disable status PCI: pciehp: Publish to user space last on probe PCI: hotplug: Demidlayer registration with the core PCI: pciehp: Drop slot workqueue PCI: pciehp: Handle events synchronously PCI: pciehp: Stop blinking on slot enable failure PCI: pciehp: Convert to threaded polling PCI: pciehp: Convert to threaded IRQ PCI: pciehp: Document struct slot and struct controller PCI: pciehp: Declare pciehp_unconfigure_device() void PCI: pciehp: Drop unnecessary NULL pointer check PCI: pciehp: Fix unprotected list iteration in IRQ handler PCI: pciehp: Fix use-after-free on unplug PCI: hotplug: Don't leak pci_slot on registration failure PCI: hotplug: Delete skeleton driver PCI: shpchp: Separate existence of SHPC and permission to use it
239 lines
5.8 KiB
C
239 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Purpose: PCI Express Port Bus Driver
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* Author: Tom Nguyen <tom.l.nguyen@intel.com>
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/init.h>
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#include <linux/aer.h>
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#include <linux/dmi.h>
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#include "../pci.h"
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#include "portdrv.h"
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/* If this switch is set, PCIe port native services should not be enabled. */
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bool pcie_ports_disabled;
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/*
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* If the user specified "pcie_ports=native", use the PCIe services regardless
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* of whether the platform has given us permission. On ACPI systems, this
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* means we ignore _OSC.
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*/
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bool pcie_ports_native;
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static int __init pcie_port_setup(char *str)
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{
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if (!strncmp(str, "compat", 6))
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pcie_ports_disabled = true;
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else if (!strncmp(str, "native", 6))
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pcie_ports_native = true;
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return 1;
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}
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__setup("pcie_ports=", pcie_port_setup);
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/* global data */
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#ifdef CONFIG_PM
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static int pcie_port_runtime_suspend(struct device *dev)
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{
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return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY;
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}
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static int pcie_port_runtime_resume(struct device *dev)
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{
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return 0;
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}
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static int pcie_port_runtime_idle(struct device *dev)
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{
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/*
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* Assume the PCI core has set bridge_d3 whenever it thinks the port
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* should be good to go to D3. Everything else, including moving
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* the port to D3, is handled by the PCI core.
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*/
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return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY;
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}
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static const struct dev_pm_ops pcie_portdrv_pm_ops = {
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.suspend = pcie_port_device_suspend,
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.resume_noirq = pcie_port_device_resume_noirq,
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.resume = pcie_port_device_resume,
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.freeze = pcie_port_device_suspend,
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.thaw = pcie_port_device_resume,
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.poweroff = pcie_port_device_suspend,
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.restore_noirq = pcie_port_device_resume_noirq,
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.restore = pcie_port_device_resume,
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.runtime_suspend = pcie_port_runtime_suspend,
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.runtime_resume = pcie_port_runtime_resume,
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.runtime_idle = pcie_port_runtime_idle,
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};
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#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
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#else /* !PM */
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#define PCIE_PORTDRV_PM_OPS NULL
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#endif /* !PM */
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/*
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* pcie_portdrv_probe - Probe PCI-Express port devices
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* @dev: PCI-Express port device being probed
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*
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* If detected invokes the pcie_port_device_register() method for
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* this port device.
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*
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*/
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static int pcie_portdrv_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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int status;
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if (!pci_is_pcie(dev) ||
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((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
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(pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
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(pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
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return -ENODEV;
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status = pcie_port_device_register(dev);
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if (status)
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return status;
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pci_save_state(dev);
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dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_SMART_SUSPEND |
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DPM_FLAG_LEAVE_SUSPENDED);
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if (pci_bridge_d3_possible(dev)) {
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/*
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* Keep the port resumed 100ms to make sure things like
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* config space accesses from userspace (lspci) will not
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* cause the port to repeatedly suspend and resume.
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*/
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pm_runtime_set_autosuspend_delay(&dev->dev, 100);
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pm_runtime_use_autosuspend(&dev->dev);
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pm_runtime_mark_last_busy(&dev->dev);
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pm_runtime_put_autosuspend(&dev->dev);
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pm_runtime_allow(&dev->dev);
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}
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return 0;
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}
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static void pcie_portdrv_remove(struct pci_dev *dev)
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{
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if (pci_bridge_d3_possible(dev)) {
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pm_runtime_forbid(&dev->dev);
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pm_runtime_get_noresume(&dev->dev);
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pm_runtime_dont_use_autosuspend(&dev->dev);
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}
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pcie_port_device_remove(dev);
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}
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static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
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enum pci_channel_state error)
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{
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/* Root Port has no impact. Always recovers. */
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return PCI_ERS_RESULT_CAN_RECOVER;
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}
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static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
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{
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return PCI_ERS_RESULT_RECOVERED;
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}
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static int resume_iter(struct device *device, void *data)
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{
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struct pcie_device *pcie_device;
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struct pcie_port_service_driver *driver;
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if (device->bus == &pcie_port_bus_type && device->driver) {
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driver = to_service_driver(device->driver);
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if (driver && driver->error_resume) {
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pcie_device = to_pcie_device(device);
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/* Forward error message to service drivers */
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driver->error_resume(pcie_device->port);
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}
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}
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return 0;
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}
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static void pcie_portdrv_err_resume(struct pci_dev *dev)
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{
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device_for_each_child(&dev->dev, NULL, resume_iter);
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}
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/*
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* LINUX Device Driver Model
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*/
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static const struct pci_device_id port_pci_ids[] = { {
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/* handle any PCI-Express port */
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PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0),
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}, { /* end: all zeroes */ }
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};
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static const struct pci_error_handlers pcie_portdrv_err_handler = {
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.error_detected = pcie_portdrv_error_detected,
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.mmio_enabled = pcie_portdrv_mmio_enabled,
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.resume = pcie_portdrv_err_resume,
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};
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static struct pci_driver pcie_portdriver = {
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.name = "pcieport",
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.id_table = &port_pci_ids[0],
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.probe = pcie_portdrv_probe,
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.remove = pcie_portdrv_remove,
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.shutdown = pcie_portdrv_remove,
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.err_handler = &pcie_portdrv_err_handler,
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.driver.pm = PCIE_PORTDRV_PM_OPS,
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};
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static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
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{
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pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
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d->ident);
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pcie_pme_disable_msi();
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return 0;
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}
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static const struct dmi_system_id pcie_portdrv_dmi_table[] __initconst = {
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/*
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* Boxes that should not use MSI for PCIe PME signaling.
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*/
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{
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.callback = dmi_pcie_pme_disable_msi,
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.ident = "MSI Wind U-100",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR,
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"MICRO-STAR INTERNATIONAL CO., LTD"),
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DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
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},
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},
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{}
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};
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static int __init pcie_portdrv_init(void)
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{
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if (pcie_ports_disabled)
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return -EACCES;
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dmi_check_system(pcie_portdrv_dmi_table);
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return pci_register_driver(&pcie_portdriver);
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}
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device_initcall(pcie_portdrv_init);
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