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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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38ea1f358b
Fix broken inline assembly contraints for cmpxchg64 on 32bit. Fixes this crash: specification exception: 0006 [#1] SMP CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.13.0 #4 task: 005a16c8 ti: 00592000 task.ti: 00592000 Krnl PSW : 070ce000 8029abd6 (lockref_get+0x3e/0x9c) ... Krnl Code: 8029abcc: a71a0001 ahi %r1,1 8029abd0: 1852 lr %r5,%r2 #8029abd2: bb40f064 cds %r4,%r0,100(%r15) >8029abd6: 1943 cr %r4,%r3 8029abd8: 1815 lr %r1,%r5 Call Trace: ([<0000000078e01870>] 0x78e01870) [<000000000021105a>] sysfs_mount+0xd2/0x1c8 [<00000000001b551e>] mount_fs+0x3a/0x134 [<00000000001ce768>] vfs_kern_mount+0x44/0x11c [<00000000001ce864>] kern_mount_data+0x24/0x3c [<00000000005cc4b8>] sysfs_init+0x74/0xd4 [<00000000005cb5b4>] mnt_init+0xe0/0x1fc [<00000000005cb16a>] vfs_caches_init+0xb6/0x14c [<00000000005be794>] start_kernel+0x318/0x33c [<000000000010001c>] _stext+0x1c/0x80 Reported-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
305 lines
7.1 KiB
C
305 lines
7.1 KiB
C
/*
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* Copyright IBM Corp. 1999, 2011
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
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*/
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#ifndef __ASM_CMPXCHG_H
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#define __ASM_CMPXCHG_H
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#include <linux/mmdebug.h>
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#include <linux/types.h>
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#include <linux/bug.h>
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, void *ptr, int size)
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{
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unsigned long addr, old;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" ((x & 0xff) << shift), "d" (~(0xff << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" ((x & 0xffff) << shift), "d" (~(0xffff << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 4:
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asm volatile(
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" l %0,%3\n"
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"0: cs %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) ptr)
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: "d" (x), "Q" (*(int *) ptr)
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: "memory", "cc");
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return old;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" lg %0,%3\n"
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"0: csg %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "Q" (*(long *) ptr)
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: "memory", "cc");
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return old;
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#endif /* CONFIG_64BIT */
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr, x) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__xchg((unsigned long)(x), (void *)(ptr), sizeof(*(ptr)));\
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__ret; \
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})
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long __cmpxchg(void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long addr, prev, tmp;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "+Q" (*(int *) addr)
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: "d" ((old & 0xff) << shift),
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"d" ((new & 0xff) << shift),
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"d" (~(0xff << shift))
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: "memory", "cc");
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "+Q" (*(int *) addr)
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: "d" ((old & 0xffff) << shift),
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"d" ((new & 0xffff) << shift),
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"d" (~(0xffff << shift))
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: "memory", "cc");
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return prev >> shift;
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case 4:
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asm volatile(
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" cs %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(int *) ptr)
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: "0" (old), "d" (new), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" csg %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(long *) ptr)
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: "0" (old), "d" (new), "Q" (*(long *) ptr)
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: "memory", "cc");
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return prev;
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#endif /* CONFIG_64BIT */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg((ptr), (unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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__ret; \
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})
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#ifdef CONFIG_64BIT
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#define cmpxchg64(ptr, o, n) \
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({ \
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cmpxchg((ptr), (o), (n)); \
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})
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#else /* CONFIG_64BIT */
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static inline unsigned long long __cmpxchg64(void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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register_pair rp_old = {.pair = old};
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register_pair rp_new = {.pair = new};
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unsigned long long *ullptr = ptr;
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asm volatile(
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" cds %0,%2,%1"
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: "+d" (rp_old), "+Q" (*ullptr)
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: "d" (rp_new)
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: "memory", "cc");
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return rp_old.pair;
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}
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#define cmpxchg64(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg64((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)); \
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__ret; \
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})
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#endif /* CONFIG_64BIT */
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#define __cmpxchg_double_op(p1, p2, o1, o2, n1, n2, insn) \
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({ \
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register __typeof__(*(p1)) __old1 asm("2") = (o1); \
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register __typeof__(*(p2)) __old2 asm("3") = (o2); \
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register __typeof__(*(p1)) __new1 asm("4") = (n1); \
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register __typeof__(*(p2)) __new2 asm("5") = (n2); \
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int cc; \
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asm volatile( \
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insn " %[old],%[new],%[ptr]\n" \
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" ipm %[cc]\n" \
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" srl %[cc],28" \
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: [cc] "=d" (cc), [old] "+d" (__old1), "+d" (__old2) \
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: [new] "d" (__new1), "d" (__new2), \
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[ptr] "Q" (*(p1)), "Q" (*(p2)) \
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: "memory", "cc"); \
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!cc; \
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})
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#define __cmpxchg_double_4(p1, p2, o1, o2, n1, n2) \
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__cmpxchg_double_op(p1, p2, o1, o2, n1, n2, "cds")
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#define __cmpxchg_double_8(p1, p2, o1, o2, n1, n2) \
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__cmpxchg_double_op(p1, p2, o1, o2, n1, n2, "cdsg")
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extern void __cmpxchg_double_called_with_bad_pointer(void);
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#define __cmpxchg_double(p1, p2, o1, o2, n1, n2) \
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({ \
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int __ret; \
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switch (sizeof(*(p1))) { \
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case 4: \
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__ret = __cmpxchg_double_4(p1, p2, o1, o2, n1, n2); \
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break; \
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case 8: \
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__ret = __cmpxchg_double_8(p1, p2, o1, o2, n1, n2); \
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break; \
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default: \
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__cmpxchg_double_called_with_bad_pointer(); \
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} \
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__ret; \
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})
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#define cmpxchg_double(p1, p2, o1, o2, n1, n2) \
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({ \
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__typeof__(p1) __p1 = (p1); \
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__typeof__(p2) __p2 = (p2); \
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int __ret; \
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BUILD_BUG_ON(sizeof(*(p1)) != sizeof(long)); \
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BUILD_BUG_ON(sizeof(*(p2)) != sizeof(long)); \
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VM_BUG_ON((unsigned long)((__p1) + 1) != (unsigned long)(__p2));\
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if (sizeof(long) == 4) \
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__ret = __cmpxchg_double_4(__p1, __p2, o1, o2, n1, n2); \
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else \
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__ret = __cmpxchg_double_8(__p1, __p2, o1, o2, n1, n2); \
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__ret; \
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})
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#define system_has_cmpxchg_double() 1
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef CONFIG_64BIT
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case 8:
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#endif
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return __cmpxchg(ptr, old, new, size);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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#define cmpxchg64_local(ptr, o, n) cmpxchg64((ptr), (o), (n))
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#endif /* __ASM_CMPXCHG_H */
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