mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 21:06:39 +07:00
871039f02f
Conflicts: drivers/net/stmmac/stmmac_main.c drivers/net/wireless/wl12xx/wl1271_cmd.c drivers/net/wireless/wl12xx/wl1271_main.c drivers/net/wireless/wl12xx/wl1271_spi.c net/core/ethtool.c net/mac80211/scan.c
233 lines
5.5 KiB
C
233 lines
5.5 KiB
C
/*
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* Bitbanged MDIO support.
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*
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* Author: Scott Wood <scottwood@freescale.com>
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* Copyright (c) 2007 Freescale Semiconductor
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*
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* Based on CPM2 MDIO code which is:
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*
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* Copyright (c) 2003 Intracom S.A.
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* by Pantelis Antoniou <panto@intracom.gr>
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*
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* 2005 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/mdio-bitbang.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#define MDIO_READ 2
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#define MDIO_WRITE 1
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#define MDIO_C45 (1<<15)
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#define MDIO_C45_ADDR (MDIO_C45 | 0)
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#define MDIO_C45_READ (MDIO_C45 | 3)
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#define MDIO_C45_WRITE (MDIO_C45 | 1)
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#define MDIO_SETUP_TIME 10
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#define MDIO_HOLD_TIME 10
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/* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY
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* is done twice per period.
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*/
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#define MDIO_DELAY 250
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/* The PHY may take up to 300 ns to produce data, plus some margin
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* for error.
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*/
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#define MDIO_READ_DELAY 350
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/* MDIO must already be configured as output. */
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static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val)
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{
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const struct mdiobb_ops *ops = ctrl->ops;
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ops->set_mdio_data(ctrl, val);
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ndelay(MDIO_DELAY);
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ops->set_mdc(ctrl, 1);
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ndelay(MDIO_DELAY);
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ops->set_mdc(ctrl, 0);
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}
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/* MDIO must already be configured as input. */
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static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl)
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{
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const struct mdiobb_ops *ops = ctrl->ops;
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ndelay(MDIO_DELAY);
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ops->set_mdc(ctrl, 1);
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ndelay(MDIO_READ_DELAY);
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ops->set_mdc(ctrl, 0);
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return ops->get_mdio_data(ctrl);
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}
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/* MDIO must already be configured as output. */
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static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits)
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{
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int i;
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for (i = bits - 1; i >= 0; i--)
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mdiobb_send_bit(ctrl, (val >> i) & 1);
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}
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/* MDIO must already be configured as input. */
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static u16 mdiobb_get_num(struct mdiobb_ctrl *ctrl, int bits)
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{
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int i;
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u16 ret = 0;
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for (i = bits - 1; i >= 0; i--) {
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ret <<= 1;
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ret |= mdiobb_get_bit(ctrl);
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}
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return ret;
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}
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/* Utility to send the preamble, address, and
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* register (common to read and write).
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*/
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static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg)
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{
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const struct mdiobb_ops *ops = ctrl->ops;
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int i;
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ops->set_mdio_dir(ctrl, 1);
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good
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* measure. The IEEE spec says this is a PHY optional
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* requirement. The AMD 79C874 requires one after power up and
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* one after a MII communications error. This means that we are
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* doing more preambles than we need, but it is safer and will be
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* much more robust.
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*/
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for (i = 0; i < 32; i++)
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mdiobb_send_bit(ctrl, 1);
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/* send the start bit (01) and the read opcode (10) or write (10).
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Clause 45 operation uses 00 for the start and 11, 10 for
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read/write */
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mdiobb_send_bit(ctrl, 0);
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if (op & MDIO_C45)
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mdiobb_send_bit(ctrl, 0);
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else
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mdiobb_send_bit(ctrl, 1);
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mdiobb_send_bit(ctrl, (op >> 1) & 1);
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mdiobb_send_bit(ctrl, (op >> 0) & 1);
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mdiobb_send_num(ctrl, phy, 5);
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mdiobb_send_num(ctrl, reg, 5);
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}
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/* In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the
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lower 16 bits of the 21 bit address. This transfer is done identically to a
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MDIO_WRITE except for a different code. To enable clause 45 mode or
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MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices
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can exist on the same bus. Normal devices should ignore the MDIO_ADDR
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phase. */
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static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr)
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{
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unsigned int dev_addr = (addr >> 16) & 0x1F;
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unsigned int reg = addr & 0xFFFF;
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mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr);
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/* send the turnaround (10) */
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mdiobb_send_bit(ctrl, 1);
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mdiobb_send_bit(ctrl, 0);
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mdiobb_send_num(ctrl, reg, 16);
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ctrl->ops->set_mdio_dir(ctrl, 0);
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mdiobb_get_bit(ctrl);
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return dev_addr;
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}
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static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
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{
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struct mdiobb_ctrl *ctrl = bus->priv;
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int ret, i;
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if (reg & MII_ADDR_C45) {
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reg = mdiobb_cmd_addr(ctrl, phy, reg);
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mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
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} else
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mdiobb_cmd(ctrl, MDIO_READ, phy, reg);
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ctrl->ops->set_mdio_dir(ctrl, 0);
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/* check the turnaround bit: the PHY should be driving it to zero */
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if (mdiobb_get_bit(ctrl) != 0) {
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/* PHY didn't drive TA low -- flush any bits it
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* may be trying to send.
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*/
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for (i = 0; i < 32; i++)
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mdiobb_get_bit(ctrl);
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return 0xffff;
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}
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ret = mdiobb_get_num(ctrl, 16);
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mdiobb_get_bit(ctrl);
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return ret;
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}
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static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
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{
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struct mdiobb_ctrl *ctrl = bus->priv;
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if (reg & MII_ADDR_C45) {
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reg = mdiobb_cmd_addr(ctrl, phy, reg);
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mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
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} else
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mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg);
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/* send the turnaround (10) */
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mdiobb_send_bit(ctrl, 1);
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mdiobb_send_bit(ctrl, 0);
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mdiobb_send_num(ctrl, val, 16);
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ctrl->ops->set_mdio_dir(ctrl, 0);
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mdiobb_get_bit(ctrl);
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return 0;
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}
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struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl)
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{
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struct mii_bus *bus;
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bus = mdiobus_alloc();
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if (!bus)
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return NULL;
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__module_get(ctrl->ops->owner);
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bus->read = mdiobb_read;
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bus->write = mdiobb_write;
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bus->priv = ctrl;
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return bus;
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}
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EXPORT_SYMBOL(alloc_mdio_bitbang);
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void free_mdio_bitbang(struct mii_bus *bus)
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{
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struct mdiobb_ctrl *ctrl = bus->priv;
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module_put(ctrl->ops->owner);
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mdiobus_free(bus);
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}
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EXPORT_SYMBOL(free_mdio_bitbang);
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MODULE_LICENSE("GPL");
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