mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 05:16:38 +07:00
d3608b6daf
CONFIG_HOTPLUG is going away as an option so __devinitdata is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Acked-by: Felipe Balbi <balbi@ti.com> Cc: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
825 lines
21 KiB
C
825 lines
21 KiB
C
/*
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* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2009 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/tegra_usb.h>
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#include <linux/irq.h>
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#include <linux/usb/otg.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/tegra_usb_phy.h>
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#define TEGRA_USB_BASE 0xC5000000
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#define TEGRA_USB2_BASE 0xC5004000
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#define TEGRA_USB3_BASE 0xC5008000
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#define TEGRA_USB_DMA_ALIGN 32
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struct tegra_ehci_hcd {
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struct ehci_hcd *ehci;
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struct tegra_usb_phy *phy;
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struct clk *clk;
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struct clk *emc_clk;
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struct usb_phy *transceiver;
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int host_resumed;
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int port_resuming;
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enum tegra_usb_phy_port_speed port_speed;
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};
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static void tegra_ehci_power_up(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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clk_prepare_enable(tegra->emc_clk);
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clk_prepare_enable(tegra->clk);
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usb_phy_set_suspend(&tegra->phy->u_phy, 0);
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tegra->host_resumed = 1;
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}
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static void tegra_ehci_power_down(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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tegra->host_resumed = 0;
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usb_phy_set_suspend(&tegra->phy->u_phy, 1);
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clk_disable_unprepare(tegra->clk);
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clk_disable_unprepare(tegra->emc_clk);
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}
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static int tegra_ehci_internal_port_reset(
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struct ehci_hcd *ehci,
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u32 __iomem *portsc_reg
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)
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{
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u32 temp;
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unsigned long flags;
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int retval = 0;
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int i, tries;
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u32 saved_usbintr;
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spin_lock_irqsave(&ehci->lock, flags);
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saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
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/* disable USB interrupt */
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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spin_unlock_irqrestore(&ehci->lock, flags);
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/*
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* Here we have to do Port Reset at most twice for
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* Port Enable bit to be set.
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*/
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for (i = 0; i < 2; i++) {
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temp = ehci_readl(ehci, portsc_reg);
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temp |= PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(10);
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temp &= ~PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(1);
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tries = 100;
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do {
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mdelay(1);
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/*
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* Up to this point, Port Enable bit is
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* expected to be set after 2 ms waiting.
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* USB1 usually takes extra 45 ms, for safety,
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* we take 100 ms as timeout.
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*/
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temp = ehci_readl(ehci, portsc_reg);
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} while (!(temp & PORT_PE) && tries--);
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if (temp & PORT_PE)
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break;
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}
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if (i == 2)
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retval = -ETIMEDOUT;
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/*
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* Clear Connect Status Change bit if it's set.
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* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
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*/
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if (temp & PORT_CSC)
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ehci_writel(ehci, PORT_CSC, portsc_reg);
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/*
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* Write to clear any interrupt status bits that might be set
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* during port reset.
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*/
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temp = ehci_readl(ehci, &ehci->regs->status);
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ehci_writel(ehci, temp, &ehci->regs->status);
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/* restore original interrupt enable bits */
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ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
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return retval;
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}
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static int tegra_ehci_hub_control(
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struct usb_hcd *hcd,
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u16 typeReq,
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u16 wValue,
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u16 wIndex,
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char *buf,
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u16 wLength
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)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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u32 __iomem *status_reg;
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u32 temp;
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unsigned long flags;
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int retval = 0;
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status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
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spin_lock_irqsave(&ehci->lock, flags);
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if (typeReq == GetPortStatus) {
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temp = ehci_readl(ehci, status_reg);
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if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
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/* Resume completed, re-enable disconnect detection */
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tegra->port_resuming = 0;
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tegra_usb_phy_postresume(tegra->phy);
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}
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}
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else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
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retval = -EPIPE;
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goto done;
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}
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temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
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temp |= PORT_WKDISC_E | PORT_WKOC_E;
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ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
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/*
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* If a transaction is in progress, there may be a delay in
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* suspending the port. Poll until the port is suspended.
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*/
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if (handshake(ehci, status_reg, PORT_SUSPEND,
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PORT_SUSPEND, 5000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
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goto done;
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}
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/* For USB1 port we need to issue Port Reset twice internally */
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if (tegra->phy->instance == 0 &&
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(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
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spin_unlock_irqrestore(&ehci->lock, flags);
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return tegra_ehci_internal_port_reset(ehci, status_reg);
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}
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/*
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* Tegra host controller will time the resume operation to clear the bit
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* when the port control state switches to HS or FS Idle. This behavior
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* is different from EHCI where the host controller driver is required
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* to set this bit to a zero after the resume duration is timed in the
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* driver.
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*/
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else if (typeReq == ClearPortFeature &&
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wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
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retval = -EPIPE;
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goto done;
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}
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if (!(temp & PORT_SUSPEND))
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goto done;
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/* Disable disconnect detection during port resume */
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tegra_usb_phy_preresume(tegra->phy);
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ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
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temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
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/* start resume signalling */
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ehci_writel(ehci, temp | PORT_RESUME, status_reg);
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set_bit(wIndex-1, &ehci->resuming_ports);
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spin_unlock_irqrestore(&ehci->lock, flags);
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msleep(20);
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spin_lock_irqsave(&ehci->lock, flags);
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/* Poll until the controller clears RESUME and SUSPEND */
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if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
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pr_err("%s: timeout waiting for RESUME\n", __func__);
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if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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ehci->reset_done[wIndex-1] = 0;
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clear_bit(wIndex-1, &ehci->resuming_ports);
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tegra->port_resuming = 1;
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goto done;
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}
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spin_unlock_irqrestore(&ehci->lock, flags);
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/* Handle the hub control events here */
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return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
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done:
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spin_unlock_irqrestore(&ehci->lock, flags);
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return retval;
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}
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static void tegra_ehci_restart(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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ehci_reset(ehci);
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/* setup the frame list and Async q heads */
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ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
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ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
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/* setup the command register and set the controller in RUN mode */
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ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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ehci->command |= CMD_RUN;
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ehci_writel(ehci, ehci->command, &ehci->regs->command);
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down_write(&ehci_cf_port_reset_rwsem);
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ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
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/* flush posted writes */
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ehci_readl(ehci, &ehci->regs->command);
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up_write(&ehci_cf_port_reset_rwsem);
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}
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static void tegra_ehci_shutdown(struct usb_hcd *hcd)
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{
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struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
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/* ehci_shutdown touches the USB controller registers, make sure
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* controller has clocks to it */
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if (!tegra->host_resumed)
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tegra_ehci_power_up(hcd);
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ehci_shutdown(hcd);
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}
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static int tegra_ehci_setup(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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/* EHCI registers start at offset 0x100 */
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ehci->caps = hcd->regs + 0x100;
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/* switch to host mode */
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hcd->has_tt = 1;
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return ehci_setup(hcd);
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}
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struct dma_aligned_buffer {
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void *kmalloc_ptr;
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void *old_xfer_buffer;
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u8 data[0];
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};
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static void free_dma_aligned_buffer(struct urb *urb)
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{
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struct dma_aligned_buffer *temp;
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if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
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return;
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temp = container_of(urb->transfer_buffer,
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struct dma_aligned_buffer, data);
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if (usb_urb_dir_in(urb))
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memcpy(temp->old_xfer_buffer, temp->data,
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urb->transfer_buffer_length);
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urb->transfer_buffer = temp->old_xfer_buffer;
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kfree(temp->kmalloc_ptr);
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urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
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}
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static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
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{
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struct dma_aligned_buffer *temp, *kmalloc_ptr;
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size_t kmalloc_size;
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if (urb->num_sgs || urb->sg ||
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urb->transfer_buffer_length == 0 ||
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!((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
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return 0;
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/* Allocate a buffer with enough padding for alignment */
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kmalloc_size = urb->transfer_buffer_length +
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sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
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kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
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if (!kmalloc_ptr)
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return -ENOMEM;
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/* Position our struct dma_aligned_buffer such that data is aligned */
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temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
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temp->kmalloc_ptr = kmalloc_ptr;
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temp->old_xfer_buffer = urb->transfer_buffer;
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if (usb_urb_dir_out(urb))
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memcpy(temp->data, urb->transfer_buffer,
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urb->transfer_buffer_length);
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urb->transfer_buffer = temp->data;
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urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
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return 0;
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}
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static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
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gfp_t mem_flags)
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{
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int ret;
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ret = alloc_dma_aligned_buffer(urb, mem_flags);
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if (ret)
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return ret;
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ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
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if (ret)
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free_dma_aligned_buffer(urb);
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return ret;
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}
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static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
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{
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usb_hcd_unmap_urb_for_dma(hcd, urb);
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free_dma_aligned_buffer(urb);
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}
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static const struct hc_driver tegra_ehci_hc_driver = {
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.description = hcd_name,
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.product_desc = "Tegra EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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.flags = HCD_USB2 | HCD_MEMORY,
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/* standard ehci functions */
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.irq = ehci_irq,
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.start = ehci_run,
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.stop = ehci_stop,
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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.get_frame_number = ehci_get_frame,
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.hub_status_data = ehci_hub_status_data,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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/* modified ehci functions for tegra */
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.reset = tegra_ehci_setup,
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.shutdown = tegra_ehci_shutdown,
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.map_urb_for_dma = tegra_ehci_map_urb_for_dma,
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.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
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.hub_control = tegra_ehci_hub_control,
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#ifdef CONFIG_PM
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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#endif
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};
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static int setup_vbus_gpio(struct platform_device *pdev,
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struct tegra_ehci_platform_data *pdata)
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{
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int err = 0;
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int gpio;
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gpio = pdata->vbus_gpio;
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if (!gpio_is_valid(gpio))
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gpio = of_get_named_gpio(pdev->dev.of_node,
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"nvidia,vbus-gpio", 0);
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if (!gpio_is_valid(gpio))
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return 0;
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err = gpio_request(gpio, "vbus_gpio");
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if (err) {
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dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
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return err;
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}
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err = gpio_direction_output(gpio, 1);
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if (err) {
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dev_err(&pdev->dev, "can't enable vbus\n");
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return err;
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}
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return err;
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}
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#ifdef CONFIG_PM
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static int controller_suspend(struct device *dev)
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{
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struct tegra_ehci_hcd *tegra =
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platform_get_drvdata(to_platform_device(dev));
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struct ehci_hcd *ehci = tegra->ehci;
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struct usb_hcd *hcd = ehci_to_hcd(ehci);
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struct ehci_regs __iomem *hw = ehci->regs;
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unsigned long flags;
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if (time_before(jiffies, ehci->next_statechange))
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msleep(10);
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ehci_halt(ehci);
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spin_lock_irqsave(&ehci->lock, flags);
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tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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spin_unlock_irqrestore(&ehci->lock, flags);
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tegra_ehci_power_down(hcd);
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return 0;
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}
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static int controller_resume(struct device *dev)
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{
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struct tegra_ehci_hcd *tegra =
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platform_get_drvdata(to_platform_device(dev));
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struct ehci_hcd *ehci = tegra->ehci;
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struct usb_hcd *hcd = ehci_to_hcd(ehci);
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struct ehci_regs __iomem *hw = ehci->regs;
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unsigned long val;
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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tegra_ehci_power_up(hcd);
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if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
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/* Wait for the phy to detect new devices
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* before we restart the controller */
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msleep(10);
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goto restart;
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}
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/* Force the phy to keep data lines in suspend state */
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tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
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|
/* Enable host mode */
|
|
tdi_reset(ehci);
|
|
|
|
/* Enable Port Power */
|
|
val = readl(&hw->port_status[0]);
|
|
val |= PORT_POWER;
|
|
writel(val, &hw->port_status[0]);
|
|
udelay(10);
|
|
|
|
/* Check if the phy resume from LP0. When the phy resume from LP0
|
|
* USB register will be reset. */
|
|
if (!readl(&hw->async_next)) {
|
|
/* Program the field PTC based on the saved speed mode */
|
|
val = readl(&hw->port_status[0]);
|
|
val &= ~PORT_TEST(~0);
|
|
if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
|
|
val |= PORT_TEST_FORCE;
|
|
else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
|
|
val |= PORT_TEST(6);
|
|
else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
|
|
val |= PORT_TEST(7);
|
|
writel(val, &hw->port_status[0]);
|
|
udelay(10);
|
|
|
|
/* Disable test mode by setting PTC field to NORMAL_OP */
|
|
val = readl(&hw->port_status[0]);
|
|
val &= ~PORT_TEST(~0);
|
|
writel(val, &hw->port_status[0]);
|
|
udelay(10);
|
|
}
|
|
|
|
/* Poll until CCS is enabled */
|
|
if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
|
|
PORT_CONNECT, 2000)) {
|
|
pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
|
|
goto restart;
|
|
}
|
|
|
|
/* Poll until PE is enabled */
|
|
if (handshake(ehci, &hw->port_status[0], PORT_PE,
|
|
PORT_PE, 2000)) {
|
|
pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
|
|
goto restart;
|
|
}
|
|
|
|
/* Clear the PCI status, to avoid an interrupt taken upon resume */
|
|
val = readl(&hw->status);
|
|
val |= STS_PCD;
|
|
writel(val, &hw->status);
|
|
|
|
/* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
|
|
val = readl(&hw->port_status[0]);
|
|
if ((val & PORT_POWER) && (val & PORT_PE)) {
|
|
val |= PORT_SUSPEND;
|
|
writel(val, &hw->port_status[0]);
|
|
|
|
/* Wait until port suspend completes */
|
|
if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
|
|
PORT_SUSPEND, 1000)) {
|
|
pr_err("%s: timeout waiting for PORT_SUSPEND\n",
|
|
__func__);
|
|
goto restart;
|
|
}
|
|
}
|
|
|
|
tegra_ehci_phy_restore_end(tegra->phy);
|
|
goto done;
|
|
|
|
restart:
|
|
if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
|
|
tegra_ehci_phy_restore_end(tegra->phy);
|
|
|
|
tegra_ehci_restart(hcd);
|
|
|
|
done:
|
|
tegra_usb_phy_preresume(tegra->phy);
|
|
tegra->port_resuming = 1;
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_ehci_suspend(struct device *dev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra =
|
|
platform_get_drvdata(to_platform_device(dev));
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
int rc = 0;
|
|
|
|
/*
|
|
* When system sleep is supported and USB controller wakeup is
|
|
* implemented: If the controller is runtime-suspended and the
|
|
* wakeup setting needs to be changed, call pm_runtime_resume().
|
|
*/
|
|
if (HCD_HW_ACCESSIBLE(hcd))
|
|
rc = controller_suspend(dev);
|
|
return rc;
|
|
}
|
|
|
|
static int tegra_ehci_resume(struct device *dev)
|
|
{
|
|
int rc;
|
|
|
|
rc = controller_resume(dev);
|
|
if (rc == 0) {
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
static int tegra_ehci_runtime_suspend(struct device *dev)
|
|
{
|
|
return controller_suspend(dev);
|
|
}
|
|
|
|
static int tegra_ehci_runtime_resume(struct device *dev)
|
|
{
|
|
return controller_resume(dev);
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra_ehci_pm_ops = {
|
|
.suspend = tegra_ehci_suspend,
|
|
.resume = tegra_ehci_resume,
|
|
.runtime_suspend = tegra_ehci_runtime_suspend,
|
|
.runtime_resume = tegra_ehci_runtime_resume,
|
|
};
|
|
|
|
#endif
|
|
|
|
static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
|
|
|
|
static int tegra_ehci_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct usb_hcd *hcd;
|
|
struct tegra_ehci_hcd *tegra;
|
|
struct tegra_ehci_platform_data *pdata;
|
|
int err = 0;
|
|
int irq;
|
|
int instance = pdev->id;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "Platform data missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Right now device-tree probed devices don't get dma_mask set.
|
|
* Since shared usb code relies on it, set it here for now.
|
|
* Once we have dma capability bindings this can go away.
|
|
*/
|
|
if (!pdev->dev.dma_mask)
|
|
pdev->dev.dma_mask = &tegra_ehci_dma_mask;
|
|
|
|
setup_vbus_gpio(pdev, pdata);
|
|
|
|
tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
|
|
GFP_KERNEL);
|
|
if (!tegra)
|
|
return -ENOMEM;
|
|
|
|
hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
|
|
dev_name(&pdev->dev));
|
|
if (!hcd) {
|
|
dev_err(&pdev->dev, "Unable to create HCD\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, tegra);
|
|
|
|
tegra->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(tegra->clk)) {
|
|
dev_err(&pdev->dev, "Can't get ehci clock\n");
|
|
err = PTR_ERR(tegra->clk);
|
|
goto fail_clk;
|
|
}
|
|
|
|
err = clk_prepare_enable(tegra->clk);
|
|
if (err)
|
|
goto fail_clk;
|
|
|
|
tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
|
|
if (IS_ERR(tegra->emc_clk)) {
|
|
dev_err(&pdev->dev, "Can't get emc clock\n");
|
|
err = PTR_ERR(tegra->emc_clk);
|
|
goto fail_emc_clk;
|
|
}
|
|
|
|
clk_prepare_enable(tegra->emc_clk);
|
|
clk_set_rate(tegra->emc_clk, 400000000);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Failed to get I/O memory\n");
|
|
err = -ENXIO;
|
|
goto fail_io;
|
|
}
|
|
hcd->rsrc_start = res->start;
|
|
hcd->rsrc_len = resource_size(res);
|
|
hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
if (!hcd->regs) {
|
|
dev_err(&pdev->dev, "Failed to remap I/O memory\n");
|
|
err = -ENOMEM;
|
|
goto fail_io;
|
|
}
|
|
|
|
/* This is pretty ugly and needs to be fixed when we do only
|
|
* device-tree probing. Old code relies on the platform_device
|
|
* numbering that we lack for device-tree-instantiated devices.
|
|
*/
|
|
if (instance < 0) {
|
|
switch (res->start) {
|
|
case TEGRA_USB_BASE:
|
|
instance = 0;
|
|
break;
|
|
case TEGRA_USB2_BASE:
|
|
instance = 1;
|
|
break;
|
|
case TEGRA_USB3_BASE:
|
|
instance = 2;
|
|
break;
|
|
default:
|
|
err = -ENODEV;
|
|
dev_err(&pdev->dev, "unknown usb instance\n");
|
|
goto fail_io;
|
|
}
|
|
}
|
|
|
|
tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
|
|
pdata->phy_config,
|
|
TEGRA_USB_PHY_MODE_HOST);
|
|
if (IS_ERR(tegra->phy)) {
|
|
dev_err(&pdev->dev, "Failed to open USB phy\n");
|
|
err = -ENXIO;
|
|
goto fail_io;
|
|
}
|
|
|
|
usb_phy_init(&tegra->phy->u_phy);
|
|
|
|
err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to power on the phy\n");
|
|
goto fail;
|
|
}
|
|
|
|
tegra->host_resumed = 1;
|
|
tegra->ehci = hcd_to_ehci(hcd);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!irq) {
|
|
dev_err(&pdev->dev, "Failed to get IRQ\n");
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (pdata->operating_mode == TEGRA_USB_OTG) {
|
|
tegra->transceiver =
|
|
devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
|
|
if (!IS_ERR_OR_NULL(tegra->transceiver))
|
|
otg_set_host(tegra->transceiver->otg, &hcd->self);
|
|
}
|
|
#endif
|
|
|
|
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to add USB HCD\n");
|
|
goto fail;
|
|
}
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
/* Don't skip the pm_runtime_forbid call if wakeup isn't working */
|
|
/* if (!pdata->power_down_on_bus_suspend) */
|
|
pm_runtime_forbid(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
return err;
|
|
|
|
fail:
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (!IS_ERR_OR_NULL(tegra->transceiver))
|
|
otg_set_host(tegra->transceiver->otg, NULL);
|
|
#endif
|
|
usb_phy_shutdown(&tegra->phy->u_phy);
|
|
fail_io:
|
|
clk_disable_unprepare(tegra->emc_clk);
|
|
fail_emc_clk:
|
|
clk_disable_unprepare(tegra->clk);
|
|
fail_clk:
|
|
usb_put_hcd(hcd);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_ehci_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
#ifdef CONFIG_USB_OTG_UTILS
|
|
if (!IS_ERR_OR_NULL(tegra->transceiver))
|
|
otg_set_host(tegra->transceiver->otg, NULL);
|
|
#endif
|
|
|
|
usb_remove_hcd(hcd);
|
|
usb_put_hcd(hcd);
|
|
|
|
usb_phy_shutdown(&tegra->phy->u_phy);
|
|
|
|
clk_disable_unprepare(tegra->clk);
|
|
|
|
clk_disable_unprepare(tegra->emc_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
|
|
|
|
if (hcd->driver->shutdown)
|
|
hcd->driver->shutdown(hcd);
|
|
}
|
|
|
|
static struct of_device_id tegra_ehci_of_match[] = {
|
|
{ .compatible = "nvidia,tegra20-ehci", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver tegra_ehci_driver = {
|
|
.probe = tegra_ehci_probe,
|
|
.remove = tegra_ehci_remove,
|
|
.shutdown = tegra_ehci_hcd_shutdown,
|
|
.driver = {
|
|
.name = "tegra-ehci",
|
|
.of_match_table = tegra_ehci_of_match,
|
|
#ifdef CONFIG_PM
|
|
.pm = &tegra_ehci_pm_ops,
|
|
#endif
|
|
}
|
|
};
|