mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 03:56:43 +07:00
43452fadd6
Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is lack of support in current release process of dma descriptor, all descriptors will be released whatever is acked or no-acked by async_tx, so there is a potential race condition when dma engine is uesd by others clients (e.g. when enable NET_DMA to offload TCP). In our case, a race condition which is raised when use both of talitos and dmaengine to offload xor is because napi scheduler will sync all pending requests in dma channels, it affects the process of raid operations due to ack_tx is not checked in fsl dma. The no-acked descriptor is freed which is submitted just now, as a dependent tx, this freed descriptor trigger BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit(). TASK = ee1a94a0[1390] 'md0_raid5' THREAD: ecf40000 CPU: 0 GPR00: 00000001 ecf41ca0 ee44/921a94a0 0000003f 00000001 c00593e4 00000000 00000001 GPR08: 00000000 a7a7a7a7 00000001 045/920000002 42028042 100a38d4 ed576d98 00000000 GPR16: ed5a11b0 00000000 2b162000 00000200 046/920000000 2d555000 ed3015e8 c15a7aa0 GPR24: 00000000 c155fc40 00000000 ecb63220 ecf41d28 e47/92f640bb0 ef640c30 ecf41ca0 NIP [c02b048c] async_tx_submit+0x6c/0x2b4 LR [c02b068c] async_tx_submit+0x26c/0x2b4 Call Trace: [ecf41ca0] [c02b068c] async_tx_submit+0x26c/0x2b448/92 (unreliable) [ecf41cd0] [c02b0a4c] async_memcpy+0x240/0x25c [ecf41d20] [c0421064] async_copy_data+0xa0/0x17c [ecf41d70] [c0421cf4] __raid_run_ops+0x874/0xe10 [ecf41df0] [c0426ee4] handle_stripe+0x820/0x25e8 [ecf41e90] [c0429080] raid5d+0x3d4/0x5b4 [ecf41f40] [c04329b8] md_thread+0x138/0x16c [ecf41f90] [c008277c] kthread+0x8c/0x90 [ecf41ff0] [c0011630] kernel_thread+0x4c/0x68 Another modification in this patch is the change of completed descriptors, there is a potential risk which caused by exception interrupt, all descriptors in ld_running list are seemed completed when an interrupt raised, it works fine under normal condition, but if there is an exception occured, it cannot work as our excepted. Hardware should not be depend on s/w list, the right way is to read current descriptor address register to find the last completed descriptor. If an interrupt is raised by an error, all descriptors in ld_running should not be seemed finished, or these unfinished descriptors in ld_running will be released wrongly. A simple way to reproduce: Enable dmatest first, then insert some bad descriptors which can trigger Programming Error interrupts before the good descriptors. Last, the good descriptors will be freed before they are processsed because of the exception intrerrupt. Note: the bad descriptors are only for simulating an exception interrupt. This case can illustrate the potential risk in current fsl-dma very well. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Qiang Liu <qiang.liu@freescale.com> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
235 lines
7.0 KiB
C
235 lines
7.0 KiB
C
/*
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __DMA_FSLDMA_H
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#define __DMA_FSLDMA_H
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#include <linux/device.h>
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#include <linux/dmapool.h>
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#include <linux/dmaengine.h>
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/* Define data structures needed by Freescale
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* MPC8540 and MPC8349 DMA controller.
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*/
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#define FSL_DMA_MR_CS 0x00000001
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#define FSL_DMA_MR_CC 0x00000002
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#define FSL_DMA_MR_CA 0x00000008
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#define FSL_DMA_MR_EIE 0x00000040
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#define FSL_DMA_MR_XFE 0x00000020
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#define FSL_DMA_MR_EOLNIE 0x00000100
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#define FSL_DMA_MR_EOLSIE 0x00000080
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#define FSL_DMA_MR_EOSIE 0x00000200
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#define FSL_DMA_MR_CDSM 0x00000010
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#define FSL_DMA_MR_CTM 0x00000004
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#define FSL_DMA_MR_EMP_EN 0x00200000
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#define FSL_DMA_MR_EMS_EN 0x00040000
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#define FSL_DMA_MR_DAHE 0x00002000
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#define FSL_DMA_MR_SAHE 0x00001000
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/*
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* Bandwidth/pause control determines how many bytes a given
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* channel is allowed to transfer before the DMA engine pauses
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* the current channel and switches to the next channel
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*/
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#define FSL_DMA_MR_BWC 0x0A000000
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/* Special MR definition for MPC8349 */
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#define FSL_DMA_MR_EOTIE 0x00000080
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#define FSL_DMA_MR_PRC_RM 0x00000800
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#define FSL_DMA_SR_CH 0x00000020
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#define FSL_DMA_SR_PE 0x00000010
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#define FSL_DMA_SR_CB 0x00000004
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#define FSL_DMA_SR_TE 0x00000080
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#define FSL_DMA_SR_EOSI 0x00000002
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#define FSL_DMA_SR_EOLSI 0x00000001
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#define FSL_DMA_SR_EOCDI 0x00000001
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#define FSL_DMA_SR_EOLNI 0x00000008
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#define FSL_DMA_SATR_SBPATMU 0x20000000
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#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
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#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
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#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
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#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
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#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
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#define FSL_DMA_DATR_DBPATMU 0x20000000
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#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
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#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
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#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
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#define FSL_DMA_EOL ((u64)0x1)
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#define FSL_DMA_SNEN ((u64)0x10)
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#define FSL_DMA_EOSIE 0x8
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#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
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#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
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#define FSL_DMA_DGSR_TE 0x80
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#define FSL_DMA_DGSR_CH 0x20
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#define FSL_DMA_DGSR_PE 0x10
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#define FSL_DMA_DGSR_EOLNI 0x08
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#define FSL_DMA_DGSR_CB 0x04
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#define FSL_DMA_DGSR_EOSI 0x02
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#define FSL_DMA_DGSR_EOLSI 0x01
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typedef u64 __bitwise v64;
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typedef u32 __bitwise v32;
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struct fsl_dma_ld_hw {
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v64 src_addr;
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v64 dst_addr;
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v64 next_ln_addr;
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v32 count;
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v32 reserve;
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} __attribute__((aligned(32)));
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struct fsl_desc_sw {
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struct fsl_dma_ld_hw hw;
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struct list_head node;
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struct list_head tx_list;
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struct dma_async_tx_descriptor async_tx;
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} __attribute__((aligned(32)));
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struct fsldma_chan_regs {
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u32 mr; /* 0x00 - Mode Register */
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u32 sr; /* 0x04 - Status Register */
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u64 cdar; /* 0x08 - Current descriptor address register */
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u64 sar; /* 0x10 - Source Address Register */
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u64 dar; /* 0x18 - Destination Address Register */
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u32 bcr; /* 0x20 - Byte Count Register */
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u64 ndar; /* 0x24 - Next Descriptor Address Register */
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};
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struct fsldma_chan;
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#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
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struct fsldma_device {
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void __iomem *regs; /* DGSR register base */
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struct device *dev;
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struct dma_device common;
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struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
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u32 feature; /* The same as DMA channels */
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int irq; /* Channel IRQ */
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};
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/* Define macros for fsldma_chan->feature property */
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#define FSL_DMA_LITTLE_ENDIAN 0x00000000
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#define FSL_DMA_BIG_ENDIAN 0x00000001
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#define FSL_DMA_IP_MASK 0x00000ff0
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#define FSL_DMA_IP_85XX 0x00000010
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#define FSL_DMA_IP_83XX 0x00000020
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#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
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#define FSL_DMA_CHAN_START_EXT 0x00002000
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#ifdef CONFIG_PM
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struct fsldma_chan_regs_save {
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u32 mr;
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};
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enum fsldma_pm_state {
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RUNNING = 0,
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SUSPENDED,
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};
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#endif
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struct fsldma_chan {
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char name[8]; /* Channel name */
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struct fsldma_chan_regs __iomem *regs;
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spinlock_t desc_lock; /* Descriptor operation lock */
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/*
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* Descriptors which are queued to run, but have not yet been
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* submitted to the hardware for execution
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*/
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struct list_head ld_pending;
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/*
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* Descriptors which are currently being executed by the hardware
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*/
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struct list_head ld_running;
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/*
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* Descriptors which have finished execution by the hardware. These
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* descriptors have already had their cleanup actions run. They are
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* waiting for the ACK bit to be set by the async_tx API.
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*/
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struct list_head ld_completed; /* Link descriptors queue */
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struct dma_chan common; /* DMA common channel */
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struct dma_pool *desc_pool; /* Descriptors pool */
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struct device *dev; /* Channel device */
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int irq; /* Channel IRQ */
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int id; /* Raw id of this channel */
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struct tasklet_struct tasklet;
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u32 feature;
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bool idle; /* DMA controller is idle */
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#ifdef CONFIG_PM
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struct fsldma_chan_regs_save regs_save;
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enum fsldma_pm_state pm_state;
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#endif
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void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
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void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
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void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
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void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
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void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
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};
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#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
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#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
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#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
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#ifndef __powerpc64__
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static u64 in_be64(const u64 __iomem *addr)
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{
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return ((u64)in_be32((u32 __iomem *)addr) << 32) |
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(in_be32((u32 __iomem *)addr + 1));
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}
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static void out_be64(u64 __iomem *addr, u64 val)
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{
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out_be32((u32 __iomem *)addr, val >> 32);
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out_be32((u32 __iomem *)addr + 1, (u32)val);
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}
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static u64 in_le64(const u64 __iomem *addr)
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{
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return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
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(in_le32((u32 __iomem *)addr));
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}
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static void out_le64(u64 __iomem *addr, u64 val)
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{
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out_le32((u32 __iomem *)addr + 1, val >> 32);
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out_le32((u32 __iomem *)addr, (u32)val);
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}
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#endif
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#define DMA_IN(fsl_chan, addr, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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in_be##width(addr) : in_le##width(addr))
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#define DMA_OUT(fsl_chan, addr, val, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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out_be##width(addr, val) : out_le##width(addr, val))
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#define DMA_TO_CPU(fsl_chan, d, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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be##width##_to_cpu((__force __be##width)(v##width)d) : \
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le##width##_to_cpu((__force __le##width)(v##width)d))
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#define CPU_TO_DMA(fsl_chan, c, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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(__force v##width)cpu_to_be##width(c) : \
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(__force v##width)cpu_to_le##width(c))
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#endif /* __DMA_FSLDMA_H */
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