mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-09 18:36:39 +07:00
4cb0e60112
It seems that starting with Skylake Xeon, channel reset clears the completion address register. Make sure the completion address register is set again after reset. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
1037 lines
27 KiB
C
1037 lines
27 KiB
C
/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2004 - 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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/*
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* This driver supports an Intel I/OAT DMA engine, which does asynchronous
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* copy operations.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/sizes.h>
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#include "dma.h"
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#include "registers.h"
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#include "hw.h"
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#include "../dmaengine.h"
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static char *chanerr_str[] = {
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"DMA Transfer Source Address Error",
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"DMA Transfer Destination Address Error",
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"Next Descriptor Address Error",
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"Descriptor Error",
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"Chan Address Value Error",
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"CHANCMD Error",
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"Chipset Uncorrectable Data Integrity Error",
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"DMA Uncorrectable Data Integrity Error",
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"Read Data Error",
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"Write Data Error",
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"Descriptor Control Error",
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"Descriptor Transfer Size Error",
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"Completion Address Error",
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"Interrupt Configuration Error",
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"Super extended descriptor Address Error",
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"Unaffiliated Error",
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"CRC or XOR P Error",
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"XOR Q Error",
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"Descriptor Count Error",
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"DIF All F detect Error",
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"Guard Tag verification Error",
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"Application Tag verification Error",
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"Reference Tag verification Error",
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"Bundle Bit Error",
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"Result DIF All F detect Error",
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"Result Guard Tag verification Error",
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"Result Application Tag verification Error",
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"Result Reference Tag verification Error",
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};
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static void ioat_eh(struct ioatdma_chan *ioat_chan);
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static void ioat_print_chanerrs(struct ioatdma_chan *ioat_chan, u32 chanerr)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(chanerr_str); i++) {
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if ((chanerr >> i) & 1) {
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dev_err(to_dev(ioat_chan), "Err(%d): %s\n",
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i, chanerr_str[i]);
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}
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}
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}
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/**
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* ioat_dma_do_interrupt - handler used for single vector interrupt mode
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* @irq: interrupt id
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* @data: interrupt data
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*/
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irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
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{
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struct ioatdma_device *instance = data;
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struct ioatdma_chan *ioat_chan;
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unsigned long attnstatus;
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int bit;
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u8 intrctrl;
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intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
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if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
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return IRQ_NONE;
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if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
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writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
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return IRQ_NONE;
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}
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attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
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for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
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ioat_chan = ioat_chan_by_index(instance, bit);
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if (test_bit(IOAT_RUN, &ioat_chan->state))
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tasklet_schedule(&ioat_chan->cleanup_task);
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}
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writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
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return IRQ_HANDLED;
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}
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/**
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* ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
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* @irq: interrupt id
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* @data: interrupt data
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*/
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irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
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{
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struct ioatdma_chan *ioat_chan = data;
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if (test_bit(IOAT_RUN, &ioat_chan->state))
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tasklet_schedule(&ioat_chan->cleanup_task);
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return IRQ_HANDLED;
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}
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void ioat_stop(struct ioatdma_chan *ioat_chan)
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{
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struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
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struct pci_dev *pdev = ioat_dma->pdev;
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int chan_id = chan_num(ioat_chan);
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struct msix_entry *msix;
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/* 1/ stop irq from firing tasklets
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* 2/ stop the tasklet from re-arming irqs
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*/
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clear_bit(IOAT_RUN, &ioat_chan->state);
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/* flush inflight interrupts */
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switch (ioat_dma->irq_mode) {
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case IOAT_MSIX:
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msix = &ioat_dma->msix_entries[chan_id];
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synchronize_irq(msix->vector);
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break;
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case IOAT_MSI:
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case IOAT_INTX:
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synchronize_irq(pdev->irq);
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break;
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default:
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break;
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}
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/* flush inflight timers */
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del_timer_sync(&ioat_chan->timer);
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/* flush inflight tasklet runs */
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tasklet_kill(&ioat_chan->cleanup_task);
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/* final cleanup now that everything is quiesced and can't re-arm */
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ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan);
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}
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static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan)
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{
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ioat_chan->dmacount += ioat_ring_pending(ioat_chan);
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ioat_chan->issued = ioat_chan->head;
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writew(ioat_chan->dmacount,
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ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
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dev_dbg(to_dev(ioat_chan),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat_chan->head, ioat_chan->tail,
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ioat_chan->issued, ioat_chan->dmacount);
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}
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void ioat_issue_pending(struct dma_chan *c)
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{
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
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if (ioat_ring_pending(ioat_chan)) {
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spin_lock_bh(&ioat_chan->prep_lock);
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__ioat_issue_pending(ioat_chan);
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spin_unlock_bh(&ioat_chan->prep_lock);
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}
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}
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/**
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* ioat_update_pending - log pending descriptors
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* @ioat: ioat+ channel
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*
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* Check if the number of unsubmitted descriptors has exceeded the
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* watermark. Called with prep_lock held
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*/
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static void ioat_update_pending(struct ioatdma_chan *ioat_chan)
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{
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if (ioat_ring_pending(ioat_chan) > ioat_pending_level)
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__ioat_issue_pending(ioat_chan);
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}
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static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan)
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{
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struct ioat_ring_ent *desc;
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struct ioat_dma_descriptor *hw;
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if (ioat_ring_space(ioat_chan) < 1) {
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dev_err(to_dev(ioat_chan),
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"Unable to start null desc - ring full\n");
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return;
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}
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dev_dbg(to_dev(ioat_chan),
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"%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued);
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desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head);
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hw = desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = 1;
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hw->ctl_f.compl_write = 1;
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/* set size to non-zero value (channel returns error when size is 0) */
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hw->size = NULL_DESC_BUFFER_SIZE;
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hw->src_addr = 0;
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hw->dst_addr = 0;
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async_tx_ack(&desc->txd);
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ioat_set_chainaddr(ioat_chan, desc->txd.phys);
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dump_desc_dbg(ioat_chan, desc);
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/* make sure descriptors are written before we submit */
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wmb();
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ioat_chan->head += 1;
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__ioat_issue_pending(ioat_chan);
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}
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void ioat_start_null_desc(struct ioatdma_chan *ioat_chan)
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{
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spin_lock_bh(&ioat_chan->prep_lock);
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if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state))
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__ioat_start_null_desc(ioat_chan);
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spin_unlock_bh(&ioat_chan->prep_lock);
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}
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static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan)
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{
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/* set the tail to be re-issued */
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ioat_chan->issued = ioat_chan->tail;
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ioat_chan->dmacount = 0;
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mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
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dev_dbg(to_dev(ioat_chan),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat_chan->head, ioat_chan->tail,
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ioat_chan->issued, ioat_chan->dmacount);
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if (ioat_ring_pending(ioat_chan)) {
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struct ioat_ring_ent *desc;
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desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail);
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ioat_set_chainaddr(ioat_chan, desc->txd.phys);
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__ioat_issue_pending(ioat_chan);
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} else
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__ioat_start_null_desc(ioat_chan);
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}
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static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo)
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{
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unsigned long end = jiffies + tmo;
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int err = 0;
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u32 status;
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status = ioat_chansts(ioat_chan);
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if (is_ioat_active(status) || is_ioat_idle(status))
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ioat_suspend(ioat_chan);
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while (is_ioat_active(status) || is_ioat_idle(status)) {
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if (tmo && time_after(jiffies, end)) {
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err = -ETIMEDOUT;
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break;
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}
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status = ioat_chansts(ioat_chan);
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cpu_relax();
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}
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return err;
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}
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static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo)
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{
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unsigned long end = jiffies + tmo;
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int err = 0;
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ioat_reset(ioat_chan);
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while (ioat_reset_pending(ioat_chan)) {
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if (end && time_after(jiffies, end)) {
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err = -ETIMEDOUT;
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break;
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}
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cpu_relax();
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}
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return err;
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}
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static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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__releases(&ioat_chan->prep_lock)
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{
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struct dma_chan *c = tx->chan;
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
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dma_cookie_t cookie;
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cookie = dma_cookie_assign(tx);
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dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie);
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if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state))
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mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
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/* make descriptor updates visible before advancing ioat->head,
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* this is purposefully not smp_wmb() since we are also
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* publishing the descriptor updates to a dma device
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*/
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wmb();
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ioat_chan->head += ioat_chan->produce;
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ioat_update_pending(ioat_chan);
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spin_unlock_bh(&ioat_chan->prep_lock);
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return cookie;
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}
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static struct ioat_ring_ent *
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ioat_alloc_ring_ent(struct dma_chan *chan, int idx, gfp_t flags)
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{
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struct ioat_dma_descriptor *hw;
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struct ioat_ring_ent *desc;
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struct ioatdma_chan *ioat_chan = to_ioat_chan(chan);
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int chunk;
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dma_addr_t phys;
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u8 *pos;
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off_t offs;
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chunk = idx / IOAT_DESCS_PER_2M;
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idx &= (IOAT_DESCS_PER_2M - 1);
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offs = idx * IOAT_DESC_SZ;
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pos = (u8 *)ioat_chan->descs[chunk].virt + offs;
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phys = ioat_chan->descs[chunk].hw + offs;
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hw = (struct ioat_dma_descriptor *)pos;
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memset(hw, 0, sizeof(*hw));
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desc = kmem_cache_zalloc(ioat_cache, flags);
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if (!desc)
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return NULL;
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = ioat_tx_submit_unlock;
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desc->hw = hw;
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desc->txd.phys = phys;
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return desc;
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}
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void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
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{
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kmem_cache_free(ioat_cache, desc);
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}
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struct ioat_ring_ent **
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ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
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{
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
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struct ioat_ring_ent **ring;
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int total_descs = 1 << order;
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int i, chunks;
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/* allocate the array to hold the software ring */
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ring = kcalloc(total_descs, sizeof(*ring), flags);
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if (!ring)
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return NULL;
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ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M;
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for (i = 0; i < chunks; i++) {
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struct ioat_descs *descs = &ioat_chan->descs[i];
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descs->virt = dma_alloc_coherent(to_dev(ioat_chan),
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SZ_2M, &descs->hw, flags);
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if (!descs->virt && (i > 0)) {
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int idx;
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for (idx = 0; idx < i; idx++) {
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dma_free_coherent(to_dev(ioat_chan), SZ_2M,
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descs->virt, descs->hw);
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descs->virt = NULL;
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descs->hw = 0;
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}
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ioat_chan->desc_chunks = 0;
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kfree(ring);
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return NULL;
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}
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}
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for (i = 0; i < total_descs; i++) {
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ring[i] = ioat_alloc_ring_ent(c, i, flags);
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if (!ring[i]) {
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int idx;
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while (i--)
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ioat_free_ring_ent(ring[i], c);
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for (idx = 0; idx < ioat_chan->desc_chunks; idx++) {
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dma_free_coherent(to_dev(ioat_chan),
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SZ_2M,
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ioat_chan->descs[idx].virt,
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ioat_chan->descs[idx].hw);
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ioat_chan->descs[idx].virt = NULL;
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ioat_chan->descs[idx].hw = 0;
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}
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ioat_chan->desc_chunks = 0;
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kfree(ring);
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return NULL;
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}
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set_desc_id(ring[i], i);
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}
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/* link descs */
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for (i = 0; i < total_descs-1; i++) {
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struct ioat_ring_ent *next = ring[i+1];
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struct ioat_dma_descriptor *hw = ring[i]->hw;
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hw->next = next->txd.phys;
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}
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ring[i]->hw->next = ring[0]->txd.phys;
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return ring;
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}
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/**
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* ioat_check_space_lock - verify space and grab ring producer lock
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* @ioat: ioat,3 channel (ring) to operate on
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* @num_descs: allocation length
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*/
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int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs)
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__acquires(&ioat_chan->prep_lock)
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{
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spin_lock_bh(&ioat_chan->prep_lock);
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/* never allow the last descriptor to be consumed, we need at
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* least one free at all times to allow for on-the-fly ring
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* resizing.
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*/
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if (likely(ioat_ring_space(ioat_chan) > num_descs)) {
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dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n",
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__func__, num_descs, ioat_chan->head,
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ioat_chan->tail, ioat_chan->issued);
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ioat_chan->produce = num_descs;
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return 0; /* with ioat->prep_lock held */
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}
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spin_unlock_bh(&ioat_chan->prep_lock);
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dev_dbg_ratelimited(to_dev(ioat_chan),
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"%s: ring full! num_descs: %d (%x:%x:%x)\n",
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__func__, num_descs, ioat_chan->head,
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ioat_chan->tail, ioat_chan->issued);
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/* progress reclaim in the allocation failure case we may be
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* called under bh_disabled so we need to trigger the timer
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* event directly
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*/
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if (time_is_before_jiffies(ioat_chan->timer.expires)
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&& timer_pending(&ioat_chan->timer)) {
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mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
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ioat_timer_event(&ioat_chan->timer);
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}
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return -ENOMEM;
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}
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static bool desc_has_ext(struct ioat_ring_ent *desc)
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{
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struct ioat_dma_descriptor *hw = desc->hw;
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|
|
if (hw->ctl_f.op == IOAT_OP_XOR ||
|
|
hw->ctl_f.op == IOAT_OP_XOR_VAL) {
|
|
struct ioat_xor_descriptor *xor = desc->xor;
|
|
|
|
if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
|
|
return true;
|
|
} else if (hw->ctl_f.op == IOAT_OP_PQ ||
|
|
hw->ctl_f.op == IOAT_OP_PQ_VAL) {
|
|
struct ioat_pq_descriptor *pq = desc->pq;
|
|
|
|
if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static void
|
|
ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed)
|
|
{
|
|
if (!sed)
|
|
return;
|
|
|
|
dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma);
|
|
kmem_cache_free(ioat_sed_cache, sed);
|
|
}
|
|
|
|
static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
u64 phys_complete;
|
|
u64 completion;
|
|
|
|
completion = *ioat_chan->completion;
|
|
phys_complete = ioat_chansts_to_addr(completion);
|
|
|
|
dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__,
|
|
(unsigned long long) phys_complete);
|
|
|
|
return phys_complete;
|
|
}
|
|
|
|
static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan,
|
|
u64 *phys_complete)
|
|
{
|
|
*phys_complete = ioat_get_current_completion(ioat_chan);
|
|
if (*phys_complete == ioat_chan->last_completion)
|
|
return false;
|
|
|
|
clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
|
|
mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void
|
|
desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc)
|
|
{
|
|
struct ioat_dma_descriptor *hw = desc->hw;
|
|
|
|
switch (hw->ctl_f.op) {
|
|
case IOAT_OP_PQ_VAL:
|
|
case IOAT_OP_PQ_VAL_16S:
|
|
{
|
|
struct ioat_pq_descriptor *pq = desc->pq;
|
|
|
|
/* check if there's error written */
|
|
if (!pq->dwbes_f.wbes)
|
|
return;
|
|
|
|
/* need to set a chanerr var for checking to clear later */
|
|
|
|
if (pq->dwbes_f.p_val_err)
|
|
*desc->result |= SUM_CHECK_P_RESULT;
|
|
|
|
if (pq->dwbes_f.q_val_err)
|
|
*desc->result |= SUM_CHECK_Q_RESULT;
|
|
|
|
return;
|
|
}
|
|
default:
|
|
return;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* __cleanup - reclaim used descriptors
|
|
* @ioat: channel (ring) to clean
|
|
*/
|
|
static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete)
|
|
{
|
|
struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
|
|
struct ioat_ring_ent *desc;
|
|
bool seen_current = false;
|
|
int idx = ioat_chan->tail, i;
|
|
u16 active;
|
|
|
|
dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n",
|
|
__func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued);
|
|
|
|
/*
|
|
* At restart of the channel, the completion address and the
|
|
* channel status will be 0 due to starting a new chain. Since
|
|
* it's new chain and the first descriptor "fails", there is
|
|
* nothing to clean up. We do not want to reap the entire submitted
|
|
* chain due to this 0 address value and then BUG.
|
|
*/
|
|
if (!phys_complete)
|
|
return;
|
|
|
|
active = ioat_ring_active(ioat_chan);
|
|
for (i = 0; i < active && !seen_current; i++) {
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1));
|
|
desc = ioat_get_ring_ent(ioat_chan, idx + i);
|
|
dump_desc_dbg(ioat_chan, desc);
|
|
|
|
/* set err stat if we are using dwbes */
|
|
if (ioat_dma->cap & IOAT_CAP_DWBES)
|
|
desc_get_errstat(ioat_chan, desc);
|
|
|
|
tx = &desc->txd;
|
|
if (tx->cookie) {
|
|
dma_cookie_complete(tx);
|
|
dma_descriptor_unmap(tx);
|
|
dmaengine_desc_get_callback_invoke(tx, NULL);
|
|
tx->callback = NULL;
|
|
tx->callback_result = NULL;
|
|
}
|
|
|
|
if (tx->phys == phys_complete)
|
|
seen_current = true;
|
|
|
|
/* skip extended descriptors */
|
|
if (desc_has_ext(desc)) {
|
|
BUG_ON(i + 1 >= active);
|
|
i++;
|
|
}
|
|
|
|
/* cleanup super extended descriptors */
|
|
if (desc->sed) {
|
|
ioat_free_sed(ioat_dma, desc->sed);
|
|
desc->sed = NULL;
|
|
}
|
|
}
|
|
|
|
/* finish all descriptor reads before incrementing tail */
|
|
smp_mb();
|
|
ioat_chan->tail = idx + i;
|
|
/* no active descs have written a completion? */
|
|
BUG_ON(active && !seen_current);
|
|
ioat_chan->last_completion = phys_complete;
|
|
|
|
if (active - i == 0) {
|
|
dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n",
|
|
__func__);
|
|
mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
|
|
}
|
|
|
|
/* microsecond delay by sysfs variable per pending descriptor */
|
|
if (ioat_chan->intr_coalesce != ioat_chan->prev_intr_coalesce) {
|
|
writew(min((ioat_chan->intr_coalesce * (active - i)),
|
|
IOAT_INTRDELAY_MASK),
|
|
ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET);
|
|
ioat_chan->prev_intr_coalesce = ioat_chan->intr_coalesce;
|
|
}
|
|
}
|
|
|
|
static void ioat_cleanup(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
u64 phys_complete;
|
|
|
|
spin_lock_bh(&ioat_chan->cleanup_lock);
|
|
|
|
if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
|
|
__cleanup(ioat_chan, phys_complete);
|
|
|
|
if (is_ioat_halted(*ioat_chan->completion)) {
|
|
u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
|
|
if (chanerr &
|
|
(IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) {
|
|
mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
|
|
ioat_eh(ioat_chan);
|
|
}
|
|
}
|
|
|
|
spin_unlock_bh(&ioat_chan->cleanup_lock);
|
|
}
|
|
|
|
void ioat_cleanup_event(unsigned long data)
|
|
{
|
|
struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data);
|
|
|
|
ioat_cleanup(ioat_chan);
|
|
if (!test_bit(IOAT_RUN, &ioat_chan->state))
|
|
return;
|
|
writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
|
|
}
|
|
|
|
static void ioat_restart_channel(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
u64 phys_complete;
|
|
|
|
/* set the completion address register again */
|
|
writel(lower_32_bits(ioat_chan->completion_dma),
|
|
ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
|
|
writel(upper_32_bits(ioat_chan->completion_dma),
|
|
ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
|
|
|
|
ioat_quiesce(ioat_chan, 0);
|
|
if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
|
|
__cleanup(ioat_chan, phys_complete);
|
|
|
|
__ioat_restart_chan(ioat_chan);
|
|
}
|
|
|
|
|
|
static void ioat_abort_descs(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
|
|
struct ioat_ring_ent *desc;
|
|
u16 active;
|
|
int idx = ioat_chan->tail, i;
|
|
|
|
/*
|
|
* We assume that the failed descriptor has been processed.
|
|
* Now we are just returning all the remaining submitted
|
|
* descriptors to abort.
|
|
*/
|
|
active = ioat_ring_active(ioat_chan);
|
|
|
|
/* we skip the failed descriptor that tail points to */
|
|
for (i = 1; i < active; i++) {
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1));
|
|
desc = ioat_get_ring_ent(ioat_chan, idx + i);
|
|
|
|
tx = &desc->txd;
|
|
if (tx->cookie) {
|
|
struct dmaengine_result res;
|
|
|
|
dma_cookie_complete(tx);
|
|
dma_descriptor_unmap(tx);
|
|
res.result = DMA_TRANS_ABORTED;
|
|
dmaengine_desc_get_callback_invoke(tx, &res);
|
|
tx->callback = NULL;
|
|
tx->callback_result = NULL;
|
|
}
|
|
|
|
/* skip extended descriptors */
|
|
if (desc_has_ext(desc)) {
|
|
WARN_ON(i + 1 >= active);
|
|
i++;
|
|
}
|
|
|
|
/* cleanup super extended descriptors */
|
|
if (desc->sed) {
|
|
ioat_free_sed(ioat_dma, desc->sed);
|
|
desc->sed = NULL;
|
|
}
|
|
}
|
|
|
|
smp_mb(); /* finish all descriptor reads before incrementing tail */
|
|
ioat_chan->tail = idx + active;
|
|
|
|
desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail);
|
|
ioat_chan->last_completion = *ioat_chan->completion = desc->txd.phys;
|
|
}
|
|
|
|
static void ioat_eh(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
struct pci_dev *pdev = to_pdev(ioat_chan);
|
|
struct ioat_dma_descriptor *hw;
|
|
struct dma_async_tx_descriptor *tx;
|
|
u64 phys_complete;
|
|
struct ioat_ring_ent *desc;
|
|
u32 err_handled = 0;
|
|
u32 chanerr_int;
|
|
u32 chanerr;
|
|
bool abort = false;
|
|
struct dmaengine_result res;
|
|
|
|
/* cleanup so tail points to descriptor that caused the error */
|
|
if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
|
|
__cleanup(ioat_chan, phys_complete);
|
|
|
|
chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int);
|
|
|
|
dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n",
|
|
__func__, chanerr, chanerr_int);
|
|
|
|
desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail);
|
|
hw = desc->hw;
|
|
dump_desc_dbg(ioat_chan, desc);
|
|
|
|
switch (hw->ctl_f.op) {
|
|
case IOAT_OP_XOR_VAL:
|
|
if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
|
|
*desc->result |= SUM_CHECK_P_RESULT;
|
|
err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
|
|
}
|
|
break;
|
|
case IOAT_OP_PQ_VAL:
|
|
case IOAT_OP_PQ_VAL_16S:
|
|
if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
|
|
*desc->result |= SUM_CHECK_P_RESULT;
|
|
err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
|
|
}
|
|
if (chanerr & IOAT_CHANERR_XOR_Q_ERR) {
|
|
*desc->result |= SUM_CHECK_Q_RESULT;
|
|
err_handled |= IOAT_CHANERR_XOR_Q_ERR;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (chanerr & IOAT_CHANERR_RECOVER_MASK) {
|
|
if (chanerr & IOAT_CHANERR_READ_DATA_ERR) {
|
|
res.result = DMA_TRANS_READ_FAILED;
|
|
err_handled |= IOAT_CHANERR_READ_DATA_ERR;
|
|
} else if (chanerr & IOAT_CHANERR_WRITE_DATA_ERR) {
|
|
res.result = DMA_TRANS_WRITE_FAILED;
|
|
err_handled |= IOAT_CHANERR_WRITE_DATA_ERR;
|
|
}
|
|
|
|
abort = true;
|
|
} else
|
|
res.result = DMA_TRANS_NOERROR;
|
|
|
|
/* fault on unhandled error or spurious halt */
|
|
if (chanerr ^ err_handled || chanerr == 0) {
|
|
dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n",
|
|
__func__, chanerr, err_handled);
|
|
dev_err(to_dev(ioat_chan), "Errors handled:\n");
|
|
ioat_print_chanerrs(ioat_chan, err_handled);
|
|
dev_err(to_dev(ioat_chan), "Errors not handled:\n");
|
|
ioat_print_chanerrs(ioat_chan, (chanerr & ~err_handled));
|
|
|
|
BUG();
|
|
}
|
|
|
|
/* cleanup the faulty descriptor since we are continuing */
|
|
tx = &desc->txd;
|
|
if (tx->cookie) {
|
|
dma_cookie_complete(tx);
|
|
dma_descriptor_unmap(tx);
|
|
dmaengine_desc_get_callback_invoke(tx, &res);
|
|
tx->callback = NULL;
|
|
tx->callback_result = NULL;
|
|
}
|
|
|
|
/* mark faulting descriptor as complete */
|
|
*ioat_chan->completion = desc->txd.phys;
|
|
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
/* we need abort all descriptors */
|
|
if (abort) {
|
|
ioat_abort_descs(ioat_chan);
|
|
/* clean up the channel, we could be in weird state */
|
|
ioat_reset_hw(ioat_chan);
|
|
}
|
|
|
|
writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int);
|
|
|
|
ioat_restart_channel(ioat_chan);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
}
|
|
|
|
static void check_active(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
if (ioat_ring_active(ioat_chan)) {
|
|
mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
|
|
return;
|
|
}
|
|
|
|
if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state))
|
|
mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
|
|
}
|
|
|
|
void ioat_timer_event(struct timer_list *t)
|
|
{
|
|
struct ioatdma_chan *ioat_chan = from_timer(ioat_chan, t, timer);
|
|
dma_addr_t phys_complete;
|
|
u64 status;
|
|
|
|
status = ioat_chansts(ioat_chan);
|
|
|
|
/* when halted due to errors check for channel
|
|
* programming errors before advancing the completion state
|
|
*/
|
|
if (is_ioat_halted(status)) {
|
|
u32 chanerr;
|
|
|
|
chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n",
|
|
__func__, chanerr);
|
|
dev_err(to_dev(ioat_chan), "Errors:\n");
|
|
ioat_print_chanerrs(ioat_chan, chanerr);
|
|
|
|
if (test_bit(IOAT_RUN, &ioat_chan->state)) {
|
|
spin_lock_bh(&ioat_chan->cleanup_lock);
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
|
|
ioat_abort_descs(ioat_chan);
|
|
dev_warn(to_dev(ioat_chan), "Reset channel...\n");
|
|
ioat_reset_hw(ioat_chan);
|
|
dev_warn(to_dev(ioat_chan), "Restart channel...\n");
|
|
ioat_restart_channel(ioat_chan);
|
|
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
spin_unlock_bh(&ioat_chan->cleanup_lock);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
spin_lock_bh(&ioat_chan->cleanup_lock);
|
|
|
|
/* handle the no-actives case */
|
|
if (!ioat_ring_active(ioat_chan)) {
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
check_active(ioat_chan);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
spin_unlock_bh(&ioat_chan->cleanup_lock);
|
|
return;
|
|
}
|
|
|
|
/* if we haven't made progress and we have already
|
|
* acknowledged a pending completion once, then be more
|
|
* forceful with a restart
|
|
*/
|
|
if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
|
|
__cleanup(ioat_chan, phys_complete);
|
|
else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) {
|
|
u32 chanerr;
|
|
|
|
chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
dev_err(to_dev(ioat_chan), "CHANSTS: %#Lx CHANERR: %#x\n",
|
|
status, chanerr);
|
|
dev_err(to_dev(ioat_chan), "Errors:\n");
|
|
ioat_print_chanerrs(ioat_chan, chanerr);
|
|
|
|
dev_dbg(to_dev(ioat_chan), "Active descriptors: %d\n",
|
|
ioat_ring_active(ioat_chan));
|
|
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
|
|
ioat_abort_descs(ioat_chan);
|
|
dev_warn(to_dev(ioat_chan), "Resetting channel...\n");
|
|
ioat_reset_hw(ioat_chan);
|
|
dev_warn(to_dev(ioat_chan), "Restarting channel...\n");
|
|
ioat_restart_channel(ioat_chan);
|
|
|
|
spin_lock_bh(&ioat_chan->prep_lock);
|
|
clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
|
|
spin_unlock_bh(&ioat_chan->prep_lock);
|
|
spin_unlock_bh(&ioat_chan->cleanup_lock);
|
|
return;
|
|
} else
|
|
set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
|
|
|
|
mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
|
|
spin_unlock_bh(&ioat_chan->cleanup_lock);
|
|
}
|
|
|
|
enum dma_status
|
|
ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
|
|
enum dma_status ret;
|
|
|
|
ret = dma_cookie_status(c, cookie, txstate);
|
|
if (ret == DMA_COMPLETE)
|
|
return ret;
|
|
|
|
ioat_cleanup(ioat_chan);
|
|
|
|
return dma_cookie_status(c, cookie, txstate);
|
|
}
|
|
|
|
int ioat_reset_hw(struct ioatdma_chan *ioat_chan)
|
|
{
|
|
/* throw away whatever the channel was doing and get it
|
|
* initialized, with ioat3 specific workarounds
|
|
*/
|
|
struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
|
|
struct pci_dev *pdev = ioat_dma->pdev;
|
|
u32 chanerr;
|
|
u16 dev_id;
|
|
int err;
|
|
|
|
ioat_quiesce(ioat_chan, msecs_to_jiffies(100));
|
|
|
|
chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
|
|
if (ioat_dma->version < IOAT_VER_3_3) {
|
|
/* clear any pending errors */
|
|
err = pci_read_config_dword(pdev,
|
|
IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
|
|
if (err) {
|
|
dev_err(&pdev->dev,
|
|
"channel error register unreachable\n");
|
|
return err;
|
|
}
|
|
pci_write_config_dword(pdev,
|
|
IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
|
|
|
|
/* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
|
|
* (workaround for spurious config parity error after restart)
|
|
*/
|
|
pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
|
|
if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
|
|
pci_write_config_dword(pdev,
|
|
IOAT_PCI_DMAUNCERRSTS_OFFSET,
|
|
0x10);
|
|
}
|
|
}
|
|
|
|
if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) {
|
|
ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000);
|
|
ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008);
|
|
ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800);
|
|
}
|
|
|
|
|
|
err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200));
|
|
if (!err) {
|
|
if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) {
|
|
writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000);
|
|
writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008);
|
|
writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800);
|
|
}
|
|
}
|
|
|
|
if (err)
|
|
dev_err(&pdev->dev, "Failed to reset: %d\n", err);
|
|
|
|
return err;
|
|
}
|