Chad Reese 920cda3870 MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. ... CN38XX pass 1 required icache prefetching to be turned off. This chip never reached production and is long dead. Other processor specific icache settings are done by the bootloader. Remove these bits from the kernel. Signed-off-by: Chad Reese <kreese@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8944/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-02-20 15:32:22 +01:00
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cpu-feature-overrides.h	MIPS: Use WSBH/DSBH/DSHD on Loongson 3A	2014-09-22 13:35:46 +02:00
dma-coherence.h	MIPS: Remove unnecessary platform dma helper functions	2013-10-29 21:24:40 +01:00
gpio.h	MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB	2013-08-26 15:33:40 +02:00
irq.h	MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX	2014-06-04 22:50:42 +02:00
kernel-entry-init.h	MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.	2015-02-20 15:32:22 +01:00
spaces.h	MIPS/OCTEON: Override default address space layout.	2013-06-21 18:07:02 +02:00
war.h	MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX	2015-02-20 15:31:27 +01:00