mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:36:42 +07:00
fffcda1183
This file only contains code relevant for the northbridge gart in AMD processors. This patch renames the file to represent this fact in the filename. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
899 lines
22 KiB
C
899 lines
22 KiB
C
/*
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* Dynamic DMA mapping support for AMD Hammer.
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*
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* Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
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* This allows to use PCI devices that only support 32bit addresses on systems
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* with more than 4GB.
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*
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* See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification.
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*
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* Copyright 2002 Andi Kleen, SuSE Labs.
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* Subject to the GNU General Public License v2 only.
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*/
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#include <linux/types.h>
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#include <linux/ctype.h>
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#include <linux/agp_backend.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/topology.h>
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#include <linux/interrupt.h>
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#include <linux/bitmap.h>
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#include <linux/kdebug.h>
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#include <linux/scatterlist.h>
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#include <linux/iommu-helper.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/gfp.h>
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#include <asm/atomic.h>
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#include <asm/mtrr.h>
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#include <asm/pgtable.h>
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#include <asm/proto.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/cacheflush.h>
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#include <asm/swiotlb.h>
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#include <asm/dma.h>
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#include <asm/amd_nb.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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static unsigned long iommu_bus_base; /* GART remapping area (physical) */
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static unsigned long iommu_size; /* size of remapping area bytes */
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static unsigned long iommu_pages; /* .. and in pages */
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static u32 *iommu_gatt_base; /* Remapping table */
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static dma_addr_t bad_dma_addr;
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/*
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* If this is disabled the IOMMU will use an optimized flushing strategy
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* of only flushing when an mapping is reused. With it true the GART is
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* flushed for every mapping. Problem is that doing the lazy flush seems
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* to trigger bugs with some popular PCI cards, in particular 3ware (but
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* has been also also seen with Qlogic at least).
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*/
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static int iommu_fullflush = 1;
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/* Allocation bitmap for the remapping area: */
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static DEFINE_SPINLOCK(iommu_bitmap_lock);
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/* Guarded by iommu_bitmap_lock: */
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static unsigned long *iommu_gart_bitmap;
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static u32 gart_unmapped_entry;
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#define GPTE_VALID 1
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#define GPTE_COHERENT 2
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#define GPTE_ENCODE(x) \
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(((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
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#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
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#define EMERGENCY_PAGES 32 /* = 128KB */
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#ifdef CONFIG_AGP
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#define AGPEXTERN extern
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#else
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#define AGPEXTERN
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#endif
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/* GART can only remap to physical addresses < 1TB */
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#define GART_MAX_PHYS_ADDR (1ULL << 40)
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/* backdoor interface to AGP driver */
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AGPEXTERN int agp_memory_reserved;
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AGPEXTERN __u32 *agp_gatt_table;
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static unsigned long next_bit; /* protected by iommu_bitmap_lock */
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static bool need_flush; /* global flush state. set for each gart wrap */
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static unsigned long alloc_iommu(struct device *dev, int size,
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unsigned long align_mask)
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{
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unsigned long offset, flags;
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unsigned long boundary_size;
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unsigned long base_index;
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base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
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PAGE_SIZE) >> PAGE_SHIFT;
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boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1,
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PAGE_SIZE) >> PAGE_SHIFT;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
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size, base_index, boundary_size, align_mask);
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if (offset == -1) {
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need_flush = true;
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offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
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size, base_index, boundary_size,
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align_mask);
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}
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if (offset != -1) {
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next_bit = offset+size;
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if (next_bit >= iommu_pages) {
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next_bit = 0;
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need_flush = true;
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}
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}
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if (iommu_fullflush)
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need_flush = true;
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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return offset;
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}
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static void free_iommu(unsigned long offset, int size)
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{
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unsigned long flags;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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bitmap_clear(iommu_gart_bitmap, offset, size);
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if (offset >= next_bit)
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next_bit = offset + size;
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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}
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/*
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* Use global flush state to avoid races with multiple flushers.
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*/
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static void flush_gart(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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if (need_flush) {
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amd_flush_garts();
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need_flush = false;
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}
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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}
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#ifdef CONFIG_IOMMU_LEAK
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/* Debugging aid for drivers that don't free their IOMMU tables */
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static int leak_trace;
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static int iommu_leak_pages = 20;
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static void dump_leak(void)
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{
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static int dump;
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if (dump)
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return;
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dump = 1;
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show_stack(NULL, NULL);
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debug_dma_dump_mappings(NULL);
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}
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#endif
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static void iommu_full(struct device *dev, size_t size, int dir)
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{
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/*
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* Ran out of IOMMU space for this operation. This is very bad.
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* Unfortunately the drivers cannot handle this operation properly.
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* Return some non mapped prereserved space in the aperture and
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* let the Northbridge deal with it. This will result in garbage
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* in the IO operation. When the size exceeds the prereserved space
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* memory corruption will occur or random memory will be DMAed
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* out. Hopefully no network devices use single mappings that big.
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*/
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dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
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if (size > PAGE_SIZE*EMERGENCY_PAGES) {
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if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
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panic("PCI-DMA: Memory would be corrupted\n");
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if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
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panic(KERN_ERR
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"PCI-DMA: Random memory would be DMAed\n");
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}
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#ifdef CONFIG_IOMMU_LEAK
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dump_leak();
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#endif
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}
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static inline int
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need_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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return force_iommu || !dma_capable(dev, addr, size);
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}
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static inline int
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nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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return !dma_capable(dev, addr, size);
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}
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/* Map a single continuous physical area into the IOMMU.
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* Caller needs to check if the iommu is needed and flush.
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*/
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static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
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size_t size, int dir, unsigned long align_mask)
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{
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unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
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unsigned long iommu_page;
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int i;
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if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
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return bad_dma_addr;
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iommu_page = alloc_iommu(dev, npages, align_mask);
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if (iommu_page == -1) {
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if (!nonforced_iommu(dev, phys_mem, size))
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return phys_mem;
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if (panic_on_overflow)
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panic("dma_map_area overflow %lu bytes\n", size);
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iommu_full(dev, size, dir);
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return bad_dma_addr;
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}
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for (i = 0; i < npages; i++) {
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iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
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phys_mem += PAGE_SIZE;
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}
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return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
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}
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/* Map a single area into the IOMMU */
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static dma_addr_t gart_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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unsigned long bus;
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phys_addr_t paddr = page_to_phys(page) + offset;
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if (!dev)
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dev = &x86_dma_fallback_dev;
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if (!need_iommu(dev, paddr, size))
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return paddr;
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bus = dma_map_area(dev, paddr, size, dir, 0);
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flush_gart();
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return bus;
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}
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/*
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* Free a DMA mapping.
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*/
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static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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unsigned long iommu_page;
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int npages;
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int i;
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if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
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dma_addr >= iommu_bus_base + iommu_size)
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return;
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iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
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npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
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for (i = 0; i < npages; i++) {
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iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
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}
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free_iommu(iommu_page, npages);
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}
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/*
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* Wrapper for pci_unmap_single working with scatterlists.
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*/
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static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, struct dma_attrs *attrs)
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{
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struct scatterlist *s;
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int i;
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for_each_sg(sg, s, nents, i) {
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if (!s->dma_length || !s->length)
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break;
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gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL);
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}
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}
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/* Fallback for dma_map_sg in case of overflow */
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static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
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int nents, int dir)
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{
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struct scatterlist *s;
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int i;
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#ifdef CONFIG_IOMMU_DEBUG
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pr_debug("dma_map_sg overflow\n");
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#endif
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for_each_sg(sg, s, nents, i) {
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unsigned long addr = sg_phys(s);
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if (nonforced_iommu(dev, addr, s->length)) {
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addr = dma_map_area(dev, addr, s->length, dir, 0);
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if (addr == bad_dma_addr) {
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if (i > 0)
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gart_unmap_sg(dev, sg, i, dir, NULL);
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nents = 0;
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sg[0].dma_length = 0;
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break;
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}
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}
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s->dma_address = addr;
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s->dma_length = s->length;
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}
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flush_gart();
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return nents;
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}
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/* Map multiple scatterlist entries continuous into the first. */
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static int __dma_map_cont(struct device *dev, struct scatterlist *start,
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int nelems, struct scatterlist *sout,
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unsigned long pages)
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{
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unsigned long iommu_start = alloc_iommu(dev, pages, 0);
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unsigned long iommu_page = iommu_start;
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struct scatterlist *s;
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int i;
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if (iommu_start == -1)
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return -1;
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for_each_sg(start, s, nelems, i) {
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unsigned long pages, addr;
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unsigned long phys_addr = s->dma_address;
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BUG_ON(s != start && s->offset);
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if (s == start) {
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sout->dma_address = iommu_bus_base;
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sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
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sout->dma_length = s->length;
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} else {
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sout->dma_length += s->length;
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}
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addr = phys_addr;
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pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
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while (pages--) {
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iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
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addr += PAGE_SIZE;
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iommu_page++;
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}
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}
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BUG_ON(iommu_page - iommu_start != pages);
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return 0;
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}
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static inline int
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dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
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struct scatterlist *sout, unsigned long pages, int need)
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{
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if (!need) {
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BUG_ON(nelems != 1);
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sout->dma_address = start->dma_address;
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sout->dma_length = start->length;
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return 0;
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}
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return __dma_map_cont(dev, start, nelems, sout, pages);
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}
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/*
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* DMA map all entries in a scatterlist.
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* Merge chunks that have page aligned sizes into a continuous mapping.
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*/
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static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, struct dma_attrs *attrs)
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{
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struct scatterlist *s, *ps, *start_sg, *sgmap;
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int need = 0, nextneed, i, out, start;
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unsigned long pages = 0;
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unsigned int seg_size;
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unsigned int max_seg_size;
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if (nents == 0)
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return 0;
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if (!dev)
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dev = &x86_dma_fallback_dev;
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out = 0;
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start = 0;
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start_sg = sg;
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sgmap = sg;
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seg_size = 0;
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max_seg_size = dma_get_max_seg_size(dev);
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ps = NULL; /* shut up gcc */
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for_each_sg(sg, s, nents, i) {
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dma_addr_t addr = sg_phys(s);
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s->dma_address = addr;
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BUG_ON(s->length == 0);
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nextneed = need_iommu(dev, addr, s->length);
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/* Handle the previous not yet processed entries */
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if (i > start) {
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/*
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* Can only merge when the last chunk ends on a
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* page boundary and the new one doesn't have an
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* offset.
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*/
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if (!iommu_merge || !nextneed || !need || s->offset ||
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(s->length + seg_size > max_seg_size) ||
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(ps->offset + ps->length) % PAGE_SIZE) {
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if (dma_map_cont(dev, start_sg, i - start,
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sgmap, pages, need) < 0)
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goto error;
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out++;
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seg_size = 0;
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sgmap = sg_next(sgmap);
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pages = 0;
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start = i;
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start_sg = s;
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}
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}
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seg_size += s->length;
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need = nextneed;
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pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
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ps = s;
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}
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if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
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goto error;
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out++;
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flush_gart();
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if (out < nents) {
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sgmap = sg_next(sgmap);
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sgmap->dma_length = 0;
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}
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return out;
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|
error:
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flush_gart();
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gart_unmap_sg(dev, sg, out, dir, NULL);
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|
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/* When it was forced or merged try again in a dumb way */
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if (force_iommu || iommu_merge) {
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out = dma_map_sg_nonforce(dev, sg, nents, dir);
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if (out > 0)
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return out;
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}
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if (panic_on_overflow)
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panic("dma_map_sg: overflow on %lu pages\n", pages);
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|
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iommu_full(dev, pages << PAGE_SHIFT, dir);
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for_each_sg(sg, s, nents, i)
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s->dma_address = bad_dma_addr;
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return 0;
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}
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|
|
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/* allocate and map a coherent mapping */
|
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static void *
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gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
|
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gfp_t flag)
|
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{
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dma_addr_t paddr;
|
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unsigned long align_mask;
|
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struct page *page;
|
|
|
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if (force_iommu && !(flag & GFP_DMA)) {
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flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
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page = alloc_pages(flag | __GFP_ZERO, get_order(size));
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if (!page)
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return NULL;
|
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|
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align_mask = (1UL << get_order(size)) - 1;
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paddr = dma_map_area(dev, page_to_phys(page), size,
|
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DMA_BIDIRECTIONAL, align_mask);
|
|
|
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flush_gart();
|
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if (paddr != bad_dma_addr) {
|
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*dma_addr = paddr;
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return page_address(page);
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}
|
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__free_pages(page, get_order(size));
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} else
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return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
|
|
|
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return NULL;
|
|
}
|
|
|
|
/* free a coherent mapping */
|
|
static void
|
|
gart_free_coherent(struct device *dev, size_t size, void *vaddr,
|
|
dma_addr_t dma_addr)
|
|
{
|
|
gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
|
|
free_pages((unsigned long)vaddr, get_order(size));
|
|
}
|
|
|
|
static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
|
{
|
|
return (dma_addr == bad_dma_addr);
|
|
}
|
|
|
|
static int no_agp;
|
|
|
|
static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
|
|
{
|
|
unsigned long a;
|
|
|
|
if (!iommu_size) {
|
|
iommu_size = aper_size;
|
|
if (!no_agp)
|
|
iommu_size /= 2;
|
|
}
|
|
|
|
a = aper + iommu_size;
|
|
iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
|
|
|
|
if (iommu_size < 64*1024*1024) {
|
|
pr_warning(
|
|
"PCI-DMA: Warning: Small IOMMU %luMB."
|
|
" Consider increasing the AGP aperture in BIOS\n",
|
|
iommu_size >> 20);
|
|
}
|
|
|
|
return iommu_size;
|
|
}
|
|
|
|
static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
|
|
{
|
|
unsigned aper_size = 0, aper_base_32, aper_order;
|
|
u64 aper_base;
|
|
|
|
pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
|
|
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
|
|
aper_order = (aper_order >> 1) & 7;
|
|
|
|
aper_base = aper_base_32 & 0x7fff;
|
|
aper_base <<= 25;
|
|
|
|
aper_size = (32 * 1024 * 1024) << aper_order;
|
|
if (aper_base + aper_size > 0x100000000UL || !aper_size)
|
|
aper_base = 0;
|
|
|
|
*size = aper_size;
|
|
return aper_base;
|
|
}
|
|
|
|
static void enable_gart_translations(void)
|
|
{
|
|
int i;
|
|
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
|
return;
|
|
|
|
for (i = 0; i < amd_nb_num(); i++) {
|
|
struct pci_dev *dev = node_to_amd_nb(i)->misc;
|
|
|
|
enable_gart_translation(dev, __pa(agp_gatt_table));
|
|
}
|
|
|
|
/* Flush the GART-TLB to remove stale entries */
|
|
amd_flush_garts();
|
|
}
|
|
|
|
/*
|
|
* If fix_up_north_bridges is set, the north bridges have to be fixed up on
|
|
* resume in the same way as they are handled in gart_iommu_hole_init().
|
|
*/
|
|
static bool fix_up_north_bridges;
|
|
static u32 aperture_order;
|
|
static u32 aperture_alloc;
|
|
|
|
void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
|
|
{
|
|
fix_up_north_bridges = true;
|
|
aperture_order = aper_order;
|
|
aperture_alloc = aper_alloc;
|
|
}
|
|
|
|
static void gart_fixup_northbridges(void)
|
|
{
|
|
int i;
|
|
|
|
if (!fix_up_north_bridges)
|
|
return;
|
|
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
|
return;
|
|
|
|
pr_info("PCI-DMA: Restoring GART aperture settings\n");
|
|
|
|
for (i = 0; i < amd_nb_num(); i++) {
|
|
struct pci_dev *dev = node_to_amd_nb(i)->misc;
|
|
|
|
/*
|
|
* Don't enable translations just yet. That is the next
|
|
* step. Restore the pre-suspend aperture settings.
|
|
*/
|
|
gart_set_size_and_enable(dev, aperture_order);
|
|
pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
|
|
}
|
|
}
|
|
|
|
static void gart_resume(void)
|
|
{
|
|
pr_info("PCI-DMA: Resuming GART IOMMU\n");
|
|
|
|
gart_fixup_northbridges();
|
|
|
|
enable_gart_translations();
|
|
}
|
|
|
|
static struct syscore_ops gart_syscore_ops = {
|
|
.resume = gart_resume,
|
|
|
|
};
|
|
|
|
/*
|
|
* Private Northbridge GATT initialization in case we cannot use the
|
|
* AGP driver for some reason.
|
|
*/
|
|
static __init int init_amd_gatt(struct agp_kern_info *info)
|
|
{
|
|
unsigned aper_size, gatt_size, new_aper_size;
|
|
unsigned aper_base, new_aper_base;
|
|
struct pci_dev *dev;
|
|
void *gatt;
|
|
int i;
|
|
|
|
pr_info("PCI-DMA: Disabling AGP.\n");
|
|
|
|
aper_size = aper_base = info->aper_size = 0;
|
|
dev = NULL;
|
|
for (i = 0; i < amd_nb_num(); i++) {
|
|
dev = node_to_amd_nb(i)->misc;
|
|
new_aper_base = read_aperture(dev, &new_aper_size);
|
|
if (!new_aper_base)
|
|
goto nommu;
|
|
|
|
if (!aper_base) {
|
|
aper_size = new_aper_size;
|
|
aper_base = new_aper_base;
|
|
}
|
|
if (aper_size != new_aper_size || aper_base != new_aper_base)
|
|
goto nommu;
|
|
}
|
|
if (!aper_base)
|
|
goto nommu;
|
|
|
|
info->aper_base = aper_base;
|
|
info->aper_size = aper_size >> 20;
|
|
|
|
gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
|
|
gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(gatt_size));
|
|
if (!gatt)
|
|
panic("Cannot allocate GATT table");
|
|
if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
|
|
panic("Could not set GART PTEs to uncacheable pages");
|
|
|
|
agp_gatt_table = gatt;
|
|
|
|
register_syscore_ops(&gart_syscore_ops);
|
|
|
|
flush_gart();
|
|
|
|
pr_info("PCI-DMA: aperture base @ %x size %u KB\n",
|
|
aper_base, aper_size>>10);
|
|
|
|
return 0;
|
|
|
|
nommu:
|
|
/* Should not happen anymore */
|
|
pr_warning("PCI-DMA: More than 4GB of RAM and no IOMMU\n"
|
|
"falling back to iommu=soft.\n");
|
|
return -1;
|
|
}
|
|
|
|
static struct dma_map_ops gart_dma_ops = {
|
|
.map_sg = gart_map_sg,
|
|
.unmap_sg = gart_unmap_sg,
|
|
.map_page = gart_map_page,
|
|
.unmap_page = gart_unmap_page,
|
|
.alloc_coherent = gart_alloc_coherent,
|
|
.free_coherent = gart_free_coherent,
|
|
.mapping_error = gart_mapping_error,
|
|
};
|
|
|
|
static void gart_iommu_shutdown(void)
|
|
{
|
|
struct pci_dev *dev;
|
|
int i;
|
|
|
|
/* don't shutdown it if there is AGP installed */
|
|
if (!no_agp)
|
|
return;
|
|
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
|
return;
|
|
|
|
for (i = 0; i < amd_nb_num(); i++) {
|
|
u32 ctl;
|
|
|
|
dev = node_to_amd_nb(i)->misc;
|
|
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
|
|
|
|
ctl &= ~GARTEN;
|
|
|
|
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
|
|
}
|
|
}
|
|
|
|
int __init gart_iommu_init(void)
|
|
{
|
|
struct agp_kern_info info;
|
|
unsigned long iommu_start;
|
|
unsigned long aper_base, aper_size;
|
|
unsigned long start_pfn, end_pfn;
|
|
unsigned long scratch;
|
|
long i;
|
|
|
|
if (!amd_nb_has_feature(AMD_NB_GART))
|
|
return 0;
|
|
|
|
#ifndef CONFIG_AGP_AMD64
|
|
no_agp = 1;
|
|
#else
|
|
/* Makefile puts PCI initialization via subsys_initcall first. */
|
|
/* Add other AMD AGP bridge drivers here */
|
|
no_agp = no_agp ||
|
|
(agp_amd64_init() < 0) ||
|
|
(agp_copy_info(agp_bridge, &info) < 0);
|
|
#endif
|
|
|
|
if (no_iommu ||
|
|
(!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
|
|
!gart_iommu_aperture ||
|
|
(no_agp && init_amd_gatt(&info) < 0)) {
|
|
if (max_pfn > MAX_DMA32_PFN) {
|
|
pr_warning("More than 4GB of memory but GART IOMMU not available.\n");
|
|
pr_warning("falling back to iommu=soft.\n");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* need to map that range */
|
|
aper_size = info.aper_size << 20;
|
|
aper_base = info.aper_base;
|
|
end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
|
|
|
|
if (end_pfn > max_low_pfn_mapped) {
|
|
start_pfn = (aper_base>>PAGE_SHIFT);
|
|
init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
|
|
}
|
|
|
|
pr_info("PCI-DMA: using GART IOMMU.\n");
|
|
iommu_size = check_iommu_size(info.aper_base, aper_size);
|
|
iommu_pages = iommu_size >> PAGE_SHIFT;
|
|
|
|
iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(iommu_pages/8));
|
|
if (!iommu_gart_bitmap)
|
|
panic("Cannot allocate iommu bitmap\n");
|
|
|
|
#ifdef CONFIG_IOMMU_LEAK
|
|
if (leak_trace) {
|
|
int ret;
|
|
|
|
ret = dma_debug_resize_entries(iommu_pages);
|
|
if (ret)
|
|
pr_debug("PCI-DMA: Cannot trace all the entries\n");
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Out of IOMMU space handling.
|
|
* Reserve some invalid pages at the beginning of the GART.
|
|
*/
|
|
bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
|
|
|
|
pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
|
|
iommu_size >> 20);
|
|
|
|
agp_memory_reserved = iommu_size;
|
|
iommu_start = aper_size - iommu_size;
|
|
iommu_bus_base = info.aper_base + iommu_start;
|
|
bad_dma_addr = iommu_bus_base;
|
|
iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
|
|
|
|
/*
|
|
* Unmap the IOMMU part of the GART. The alias of the page is
|
|
* always mapped with cache enabled and there is no full cache
|
|
* coherency across the GART remapping. The unmapping avoids
|
|
* automatic prefetches from the CPU allocating cache lines in
|
|
* there. All CPU accesses are done via the direct mapping to
|
|
* the backing memory. The GART address is only used by PCI
|
|
* devices.
|
|
*/
|
|
set_memory_np((unsigned long)__va(iommu_bus_base),
|
|
iommu_size >> PAGE_SHIFT);
|
|
/*
|
|
* Tricky. The GART table remaps the physical memory range,
|
|
* so the CPU wont notice potential aliases and if the memory
|
|
* is remapped to UC later on, we might surprise the PCI devices
|
|
* with a stray writeout of a cacheline. So play it sure and
|
|
* do an explicit, full-scale wbinvd() _after_ having marked all
|
|
* the pages as Not-Present:
|
|
*/
|
|
wbinvd();
|
|
|
|
/*
|
|
* Now all caches are flushed and we can safely enable
|
|
* GART hardware. Doing it early leaves the possibility
|
|
* of stale cache entries that can lead to GART PTE
|
|
* errors.
|
|
*/
|
|
enable_gart_translations();
|
|
|
|
/*
|
|
* Try to workaround a bug (thanks to BenH):
|
|
* Set unmapped entries to a scratch page instead of 0.
|
|
* Any prefetches that hit unmapped entries won't get an bus abort
|
|
* then. (P2P bridge may be prefetching on DMA reads).
|
|
*/
|
|
scratch = get_zeroed_page(GFP_KERNEL);
|
|
if (!scratch)
|
|
panic("Cannot allocate iommu scratch page");
|
|
gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
|
|
for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
|
|
iommu_gatt_base[i] = gart_unmapped_entry;
|
|
|
|
flush_gart();
|
|
dma_ops = &gart_dma_ops;
|
|
x86_platform.iommu_shutdown = gart_iommu_shutdown;
|
|
swiotlb = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init gart_parse_options(char *p)
|
|
{
|
|
int arg;
|
|
|
|
#ifdef CONFIG_IOMMU_LEAK
|
|
if (!strncmp(p, "leak", 4)) {
|
|
leak_trace = 1;
|
|
p += 4;
|
|
if (*p == '=')
|
|
++p;
|
|
if (isdigit(*p) && get_option(&p, &arg))
|
|
iommu_leak_pages = arg;
|
|
}
|
|
#endif
|
|
if (isdigit(*p) && get_option(&p, &arg))
|
|
iommu_size = arg;
|
|
if (!strncmp(p, "fullflush", 9))
|
|
iommu_fullflush = 1;
|
|
if (!strncmp(p, "nofullflush", 11))
|
|
iommu_fullflush = 0;
|
|
if (!strncmp(p, "noagp", 5))
|
|
no_agp = 1;
|
|
if (!strncmp(p, "noaperture", 10))
|
|
fix_aperture = 0;
|
|
/* duplicated from pci-dma.c */
|
|
if (!strncmp(p, "force", 5))
|
|
gart_iommu_aperture_allowed = 1;
|
|
if (!strncmp(p, "allowed", 7))
|
|
gart_iommu_aperture_allowed = 1;
|
|
if (!strncmp(p, "memaper", 7)) {
|
|
fallback_aper_force = 1;
|
|
p += 7;
|
|
if (*p == '=') {
|
|
++p;
|
|
if (get_option(&p, &arg))
|
|
fallback_aper_order = arg;
|
|
}
|
|
}
|
|
}
|
|
IOMMU_INIT_POST(gart_iommu_hole_init);
|