mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 12:48:25 +07:00
916f562fb2
side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1 -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/ tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9 ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd O2zWCGffeYs= =mK0C -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
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# SPDX-License-Identifier: GPL-2.0
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config CLKDEV_LOOKUP
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bool
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select HAVE_CLK
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config HAVE_CLK_PREPARE
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bool
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config COMMON_CLK
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bool
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select HAVE_CLK_PREPARE
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select CLKDEV_LOOKUP
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select SRCU
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select RATIONAL
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---help---
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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menu "Common Clock Framework"
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depends on COMMON_CLK
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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---help---
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microelectronics.
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source "drivers/clk/versatile/Kconfig"
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config CLK_HSDK
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bool "PLL Driver for HSDK platform"
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depends on OF || COMPILE_TEST
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---help---
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This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
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control.
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config COMMON_CLK_MAX77686
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tristate "Clock driver for Maxim 77620/77686/77802 MFD"
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depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
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---help---
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This driver supports Maxim 77620/77686/77802 crystal oscillator
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clock.
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config COMMON_CLK_MAX9485
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tristate "Maxim 9485 Programmable Clock Generator"
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depends on I2C
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help
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This driver supports Maxim 9485 Programmable Audio Clock Generator
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config COMMON_CLK_RK808
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tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
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depends on MFD_RK808
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---help---
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This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
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These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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Clkout1 is always on, Clkout2 can off by control register.
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config COMMON_CLK_HI655X
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tristate "Clock driver for Hi655x" if EXPERT
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depends on (MFD_HI655X_PMIC || COMPILE_TEST)
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depends on REGMAP
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default MFD_HI655X_PMIC
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---help---
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This driver supports the hi655x PMIC clock. This
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multi-function device has one fixed-rate oscillator, clocked
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at 32KHz.
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config COMMON_CLK_SCMI
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tristate "Clock driver controlled via SCMI interface"
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depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
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---help---
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This driver provides support for clocks that are controlled
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by firmware that implements the SCMI interface.
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This driver uses SCMI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SCPI
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tristate "Clock driver controlled via SCPI interface"
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depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
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---help---
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This driver provides support for clocks that are controlled
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by firmware that implements the SCPI interface.
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This driver uses SCPI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SI5341
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tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports Silicon Labs Si5341 and Si5340 programmable clock
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generators. Not all features of these chips are currently supported
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by the driver, in particular it only supports XTAL input. The chip can
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be pre-programmed to support other configurations and features not yet
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implemented in the driver.
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config COMMON_CLK_SI5351
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tristate "Clock driver for SiLabs 5351A/B/C"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports Silicon Labs 5351A/B/C programmable clock
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generators.
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config COMMON_CLK_SI514
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tristate "Clock driver for SiLabs 514 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports the Silicon Labs 514 programmable clock
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generator.
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config COMMON_CLK_SI544
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tristate "Clock driver for SiLabs 544 devices"
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depends on I2C
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select REGMAP_I2C
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help
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---help---
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This driver supports the Silicon Labs 544 programmable clock
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generator.
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config COMMON_CLK_SI570
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tristate "Clock driver for SiLabs 570 and compatible devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_CDCE706
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tristate "Clock driver for TI CDCE706 clock synthesizer"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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config COMMON_CLK_CDCE925
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tristate "Clock driver for TI CDCE913/925/937/949 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports the TI CDCE913/925/937/949 programmable clock
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synthesizer. Each chip has different number of PLLs and outputs.
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For example, the CDCE925 contains two PLLs with spread-spectrum
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clocking support and five output dividers. The driver only supports
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the following setup, and uses a fixed setting for the output muxes.
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Y1 is derived from the input clock
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Y2 and Y3 derive from PLL1
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Y4 and Y5 derive from PLL2
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Given a target output frequency, the driver will set the PLL and
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divider to best approximate the desired output.
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config COMMON_CLK_CS2000_CP
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tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
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depends on I2C
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help
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If you say yes here you get support for the CS2000 clock multiplier.
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config COMMON_CLK_GEMINI
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bool "Clock driver for Cortina Systems Gemini SoC"
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depends on ARCH_GEMINI || COMPILE_TEST
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select MFD_SYSCON
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select RESET_CONTROLLER
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---help---
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
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default ARCH_ASPEED
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select MFD_SYSCON
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select RESET_CONTROLLER
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---help---
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This driver supports the SoC clocks on the Aspeed BMC platforms.
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The G4 and G5 series, including the ast2400 and ast2500, are supported
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by this driver.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE || COMPILE_TEST
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---help---
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This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
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clock. These multi-function devices have two (S2MPS14) or three
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(S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
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config CLK_TWL6040
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tristate "External McPDM functional clock from twl6040"
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depends on TWL6040_CORE
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---help---
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Enable the external functional clock support on OMAP4+ platforms for
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McPDM. McPDM module is using the external bit clock on the McPDM bus
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as functional clock.
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config COMMON_CLK_AXI_CLKGEN
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tristate "AXI clkgen driver"
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depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
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help
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---help---
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Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
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FPGAs. It is commonly used in Analog Devices' reference designs.
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config CLK_QORIQ
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bool "Clock driver for Freescale QorIQ platforms"
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depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF
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---help---
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This adds the clock driver support for Freescale QorIQ platforms
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using common clock framework.
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config COMMON_CLK_XGENE
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bool "Clock driver for APM XGene SoC"
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default ARCH_XGENE
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depends on ARM64 || COMPILE_TEST
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---help---
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Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
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config COMMON_CLK_LOCHNAGAR
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tristate "Cirrus Logic Lochnagar clock driver"
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depends on MFD_LOCHNAGAR
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help
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This driver supports the clocking features of the Cirrus Logic
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Lochnagar audio development board.
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config COMMON_CLK_NXP
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def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
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select REGMAP_MMIO if ARCH_LPC32XX
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select MFD_SYSCON if ARCH_LPC18XX
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---help---
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Support for clock providers on NXP platforms.
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config COMMON_CLK_PALMAS
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tristate "Clock driver for TI Palmas devices"
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depends on MFD_PALMAS
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---help---
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This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
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using common clock framework.
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config COMMON_CLK_PWM
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tristate "Clock driver for PWMs used as clock outputs"
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depends on PWM
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---help---
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Adapter driver so that any PWM output can be (mis)used as clock signal
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at 50% duty cycle.
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config COMMON_CLK_PXA
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def_bool COMMON_CLK && ARCH_PXA
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---help---
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Support for the Marvell PXA SoC.
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config COMMON_CLK_PIC32
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def_bool COMMON_CLK && MACH_PIC32
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config COMMON_CLK_OXNAS
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bool "Clock driver for the OXNAS SoC Family"
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depends on ARCH_OXNAS || COMPILE_TEST
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select MFD_SYSCON
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---help---
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Support for the OXNAS SoC Family clocks.
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config COMMON_CLK_VC5
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tristate "Clock driver for IDT VersaClock 5,6 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports the IDT VersaClock 5 and VersaClock 6
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programmable clock generators.
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config COMMON_CLK_STM32MP157
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def_bool COMMON_CLK && MACH_STM32MP157
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help
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---help---
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Support for stm32mp157 SoC family clocks
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config COMMON_CLK_STM32F
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def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
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help
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---help---
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Support for stm32f4 and stm32f7 SoC families clocks
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config COMMON_CLK_STM32H7
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def_bool COMMON_CLK && MACH_STM32H743
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help
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---help---
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Support for stm32h7 SoC family clocks
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config COMMON_CLK_BD718XX
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tristate "Clock driver for ROHM BD718x7 PMIC"
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depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
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help
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This driver supports ROHM BD71837, ROHM BD71847 and
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ROHM BD70528 PMICs clock gates.
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config COMMON_CLK_FIXED_MMIO
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bool "Clock driver for Memory Mapped Fixed values"
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depends on COMMON_CLK && OF
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help
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Support for Memory Mapped IO Fixed clocks
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source "drivers/clk/actions/Kconfig"
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source "drivers/clk/analogbits/Kconfig"
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/imgtec/Kconfig"
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source "drivers/clk/imx/Kconfig"
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source "drivers/clk/ingenic/Kconfig"
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source "drivers/clk/keystone/Kconfig"
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source "drivers/clk/mediatek/Kconfig"
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source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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source "drivers/clk/sprd/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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endmenu
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