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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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752a6422fe
Some of the assembler files in lib/ make use of the fact that in the ELFv1 ABI, the caller guarantees to provide stack space to save the parameter registers r3 ... r10. This guarantee is no longer present in ELFv2 for functions that have no variable argument list and no more than 8 arguments. Change the affected routines to temporarily store registers in the red zone and/or the top of their own stack frame (in the space provided to save r31 .. r29, which is actually not used in these routines). In opal_query_takeover, simply always allocate a stack frame; the routine is not performance critical. Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org>
169 lines
3.5 KiB
ArmAsm
169 lines
3.5 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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_GLOBAL(copypage_power7)
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/*
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* We prefetch both the source and destination using enhanced touch
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* instructions. We use a stream ID of 0 for the load side and
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* 1 for the store side. Since source and destination are page
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* aligned we don't need to clear the bottom 7 bits of either
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* address.
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*/
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ori r9,r3,1 /* stream=1 => to */
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#ifdef CONFIG_PPC_64K_PAGES
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lis r7,0x0E01 /* depth=7
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* units/cachelines=512 */
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#else
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lis r7,0x0E00 /* depth=7 */
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ori r7,r7,0x1000 /* units/cachelines=32 */
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#endif
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ori r10,r7,1 /* stream=1 */
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lis r8,0x8000 /* GO=1 */
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clrldi r8,r8,32
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.machine push
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.machine "power4"
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/* setup read stream 0 */
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dcbt r0,r4,0b01000 /* addr from */
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dcbt r0,r7,0b01010 /* length and depth from */
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/* setup write stream 1 */
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dcbtst r0,r9,0b01000 /* addr to */
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dcbtst r0,r10,0b01010 /* length and depth to */
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eieio
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dcbt r0,r8,0b01010 /* all streams GO */
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.machine pop
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#ifdef CONFIG_ALTIVEC
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mflr r0
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std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
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std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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bl enter_vmx_copy
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cmpwi r3,0
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ld r0,STACKFRAMESIZE+16(r1)
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ld r3,STK_REG(R31)(r1)
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ld r4,STK_REG(R30)(r1)
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mtlr r0
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li r0,(PAGE_SIZE/128)
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mtctr r0
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beq .Lnonvmx_copy
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addi r1,r1,STACKFRAMESIZE
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li r6,16
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li r7,32
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li r8,48
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li r9,64
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li r10,80
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li r11,96
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li r12,112
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.align 5
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1: lvx vr7,r0,r4
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lvx vr6,r4,r6
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lvx vr5,r4,r7
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lvx vr4,r4,r8
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lvx vr3,r4,r9
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lvx vr2,r4,r10
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lvx vr1,r4,r11
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lvx vr0,r4,r12
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addi r4,r4,128
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stvx vr7,r0,r3
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stvx vr6,r3,r6
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stvx vr5,r3,r7
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stvx vr4,r3,r8
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stvx vr3,r3,r9
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stvx vr2,r3,r10
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stvx vr1,r3,r11
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stvx vr0,r3,r12
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addi r3,r3,128
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bdnz 1b
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b exit_vmx_copy /* tail call optimise */
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#else
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li r0,(PAGE_SIZE/128)
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mtctr r0
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stdu r1,-STACKFRAMESIZE(r1)
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#endif
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.Lnonvmx_copy:
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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std r17,STK_REG(R17)(r1)
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std r18,STK_REG(R18)(r1)
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std r19,STK_REG(R19)(r1)
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std r20,STK_REG(R20)(r1)
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1: ld r0,0(r4)
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ld r5,8(r4)
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ld r6,16(r4)
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ld r7,24(r4)
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ld r8,32(r4)
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ld r9,40(r4)
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ld r10,48(r4)
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ld r11,56(r4)
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ld r12,64(r4)
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ld r14,72(r4)
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ld r15,80(r4)
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ld r16,88(r4)
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ld r17,96(r4)
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ld r18,104(r4)
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ld r19,112(r4)
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ld r20,120(r4)
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addi r4,r4,128
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std r0,0(r3)
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std r5,8(r3)
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std r6,16(r3)
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std r7,24(r3)
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std r8,32(r3)
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std r9,40(r3)
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std r10,48(r3)
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std r11,56(r3)
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std r12,64(r3)
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std r14,72(r3)
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std r15,80(r3)
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std r16,88(r3)
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std r17,96(r3)
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std r18,104(r3)
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std r19,112(r3)
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std r20,120(r3)
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addi r3,r3,128
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bdnz 1b
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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ld r17,STK_REG(R17)(r1)
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ld r18,STK_REG(R18)(r1)
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ld r19,STK_REG(R19)(r1)
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ld r20,STK_REG(R20)(r1)
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addi r1,r1,STACKFRAMESIZE
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blr
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