mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 04:11:44 +07:00
fa5e5c4092
Replace the extra interrupt handling code and reuse the existing idtentry machinery. This moves the irq stack switching on 64-bit from ASM to C code; 32-bit already does the stack switching in C. This requires to remove HAVE_IRQ_EXIT_ON_IRQ_STACK as the stack switch is not longer in the low level entry code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Andy Lutomirski <luto@kernel.org> Link: https://lore.kernel.org/r/20200521202119.078690991@linutronix.de
510 lines
14 KiB
C
510 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Support of MSI, HPET and DMAR interrupts.
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*
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* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
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* Moved from arch/x86/kernel/apic/io_apic.c.
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* Jiang Liu <jiang.liu@linux.intel.com>
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* Convert to hierarchical irqdomain
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*/
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/dmar.h>
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#include <linux/hpet.h>
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#include <linux/msi.h>
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#include <asm/irqdomain.h>
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#include <asm/msidef.h>
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#include <asm/hpet.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/irq_remapping.h>
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static struct irq_domain *msi_default_domain;
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static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg)
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{
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msg->address_hi = MSI_ADDR_BASE_HI;
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if (x2apic_enabled())
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msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
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msg->address_lo =
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MSI_ADDR_BASE_LO |
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((apic->irq_dest_mode == 0) ?
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MSI_ADDR_DEST_MODE_PHYSICAL :
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MSI_ADDR_DEST_MODE_LOGICAL) |
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MSI_ADDR_REDIRECTION_CPU |
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MSI_ADDR_DEST_ID(cfg->dest_apicid);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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MSI_DATA_DELIVERY_FIXED |
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MSI_DATA_VECTOR(cfg->vector);
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}
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static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
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{
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__irq_msi_compose_msg(irqd_cfg(data), msg);
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}
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static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
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{
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struct msi_msg msg[2] = { [1] = { }, };
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__irq_msi_compose_msg(cfg, msg);
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irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
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}
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static int
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msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
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{
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struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
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struct irq_data *parent = irqd->parent_data;
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unsigned int cpu;
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int ret;
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/* Save the current configuration */
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cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
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old_cfg = *cfg;
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/* Allocate a new target vector */
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
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return ret;
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/*
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* For non-maskable and non-remapped MSI interrupts the migration
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* to a different destination CPU and a different vector has to be
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* done careful to handle the possible stray interrupt which can be
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* caused by the non-atomic update of the address/data pair.
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*
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* Direct update is possible when:
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* - The MSI is maskable (remapped MSI does not use this code path)).
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* The quirk bit is not set in this case.
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* - The new vector is the same as the old vector
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* - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
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* - The new destination CPU is the same as the old destination CPU
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*/
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if (!irqd_msi_nomask_quirk(irqd) ||
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cfg->vector == old_cfg.vector ||
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old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
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cfg->dest_apicid == old_cfg.dest_apicid) {
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irq_msi_update_msg(irqd, cfg);
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return ret;
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}
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/*
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* Paranoia: Validate that the interrupt target is the local
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* CPU.
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*/
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if (WARN_ON_ONCE(cpu != smp_processor_id())) {
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irq_msi_update_msg(irqd, cfg);
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return ret;
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}
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/*
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* Redirect the interrupt to the new vector on the current CPU
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* first. This might cause a spurious interrupt on this vector if
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* the device raises an interrupt right between this update and the
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* update to the final destination CPU.
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*
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* If the vector is in use then the installed device handler will
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* denote it as spurious which is no harm as this is a rare event
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* and interrupt handlers have to cope with spurious interrupts
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* anyway. If the vector is unused, then it is marked so it won't
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* trigger the 'No irq handler for vector' warning in
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* common_interrupt().
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*
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* This requires to hold vector lock to prevent concurrent updates to
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* the affected vector.
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*/
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lock_vector_lock();
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/*
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* Mark the new target vector on the local CPU if it is currently
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* unused. Reuse the VECTOR_RETRIGGERED state which is also used in
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* the CPU hotplug path for a similar purpose. This cannot be
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* undone here as the current CPU has interrupts disabled and
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* cannot handle the interrupt before the whole set_affinity()
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* section is done. In the CPU unplug case, the current CPU is
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* about to vanish and will not handle any interrupts anymore. The
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* vector is cleaned up when the CPU comes online again.
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*/
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if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
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this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
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/* Redirect it to the new vector on the local CPU temporarily */
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old_cfg.vector = cfg->vector;
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irq_msi_update_msg(irqd, &old_cfg);
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/* Now transition it to the target CPU */
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irq_msi_update_msg(irqd, cfg);
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/*
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* All interrupts after this point are now targeted at the new
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* vector/CPU.
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*
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* Drop vector lock before testing whether the temporary assignment
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* to the local CPU was hit by an interrupt raised in the device,
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* because the retrigger function acquires vector lock again.
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*/
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unlock_vector_lock();
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/*
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* Check whether the transition raced with a device interrupt and
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* is pending in the local APICs IRR. It is safe to do this outside
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* of vector lock as the irq_desc::lock of this interrupt is still
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* held and interrupts are disabled: The check is not accessing the
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* underlying vector store. It's just checking the local APIC's
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* IRR.
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*/
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if (lapic_vector_set_in_irr(cfg->vector))
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irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
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return ret;
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}
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/*
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* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
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* which implement the MSI or MSI-X Capability Structure.
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*/
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static struct irq_chip pci_msi_controller = {
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.name = "PCI-MSI",
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.irq_unmask = pci_msi_unmask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_compose_msi_msg = irq_msi_compose_msg,
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.irq_set_affinity = msi_set_affinity,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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struct irq_domain *domain;
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struct irq_alloc_info info;
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init_irq_alloc_info(&info, NULL);
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info.type = X86_IRQ_ALLOC_TYPE_MSI;
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info.msi_dev = dev;
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domain = irq_remapping_get_irq_domain(&info);
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if (domain == NULL)
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domain = msi_default_domain;
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if (domain == NULL)
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return -ENOSYS;
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return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
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}
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void native_teardown_msi_irq(unsigned int irq)
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{
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irq_domain_free_irqs(irq, 1);
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}
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static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
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msi_alloc_info_t *arg)
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{
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return arg->msi_hwirq;
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}
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int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
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msi_alloc_info_t *arg)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct msi_desc *desc = first_pci_msi_entry(pdev);
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init_irq_alloc_info(arg, NULL);
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arg->msi_dev = pdev;
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if (desc->msi_attrib.is_msix) {
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arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
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} else {
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arg->type = X86_IRQ_ALLOC_TYPE_MSI;
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arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_msi_prepare);
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void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
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{
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arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
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}
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EXPORT_SYMBOL_GPL(pci_msi_set_desc);
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static struct msi_domain_ops pci_msi_domain_ops = {
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.get_hwirq = pci_msi_get_hwirq,
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.msi_prepare = pci_msi_prepare,
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.set_desc = pci_msi_set_desc,
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};
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static struct msi_domain_info pci_msi_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX,
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.ops = &pci_msi_domain_ops,
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.chip = &pci_msi_controller,
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.handler = handle_edge_irq,
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.handler_name = "edge",
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};
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void __init arch_init_msi_domain(struct irq_domain *parent)
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{
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struct fwnode_handle *fn;
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if (disable_apic)
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return;
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fn = irq_domain_alloc_named_fwnode("PCI-MSI");
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if (fn) {
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msi_default_domain =
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pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
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parent);
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irq_domain_free_fwnode(fn);
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}
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if (!msi_default_domain)
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pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
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else
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msi_default_domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
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}
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#ifdef CONFIG_IRQ_REMAP
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static struct irq_chip pci_msi_ir_controller = {
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.name = "IR-PCI-MSI",
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.irq_unmask = pci_msi_unmask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static struct msi_domain_info pci_msi_ir_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
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.ops = &pci_msi_domain_ops,
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.chip = &pci_msi_ir_controller,
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.handler = handle_edge_irq,
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.handler_name = "edge",
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};
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struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
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const char *name, int id)
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{
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struct fwnode_handle *fn;
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struct irq_domain *d;
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fn = irq_domain_alloc_named_id_fwnode(name, id);
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if (!fn)
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return NULL;
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d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
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irq_domain_free_fwnode(fn);
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return d;
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}
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#endif
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#ifdef CONFIG_DMAR_TABLE
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static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
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{
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dmar_msi_write(data->irq, msg);
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}
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static struct irq_chip dmar_msi_controller = {
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.name = "DMAR-MSI",
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.irq_unmask = dmar_msi_unmask,
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.irq_mask = dmar_msi_mask,
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.irq_ack = irq_chip_ack_parent,
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.irq_set_affinity = msi_domain_set_affinity,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_compose_msi_msg = irq_msi_compose_msg,
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.irq_write_msi_msg = dmar_msi_write_msg,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
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msi_alloc_info_t *arg)
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{
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return arg->dmar_id;
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}
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static int dmar_msi_init(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq,
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irq_hw_number_t hwirq, msi_alloc_info_t *arg)
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{
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irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
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handle_edge_irq, arg->dmar_data, "edge");
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return 0;
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}
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static struct msi_domain_ops dmar_msi_domain_ops = {
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.get_hwirq = dmar_msi_get_hwirq,
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.msi_init = dmar_msi_init,
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};
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static struct msi_domain_info dmar_msi_domain_info = {
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.ops = &dmar_msi_domain_ops,
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.chip = &dmar_msi_controller,
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};
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static struct irq_domain *dmar_get_irq_domain(void)
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{
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static struct irq_domain *dmar_domain;
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static DEFINE_MUTEX(dmar_lock);
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struct fwnode_handle *fn;
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mutex_lock(&dmar_lock);
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if (dmar_domain)
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goto out;
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fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
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if (fn) {
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dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
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x86_vector_domain);
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irq_domain_free_fwnode(fn);
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}
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out:
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mutex_unlock(&dmar_lock);
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return dmar_domain;
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}
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int dmar_alloc_hwirq(int id, int node, void *arg)
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{
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struct irq_domain *domain = dmar_get_irq_domain();
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struct irq_alloc_info info;
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if (!domain)
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return -1;
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init_irq_alloc_info(&info, NULL);
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info.type = X86_IRQ_ALLOC_TYPE_DMAR;
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info.dmar_id = id;
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info.dmar_data = arg;
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return irq_domain_alloc_irqs(domain, 1, node, &info);
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}
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void dmar_free_hwirq(int irq)
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{
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irq_domain_free_irqs(irq, 1);
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}
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#endif
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/*
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* MSI message composition
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*/
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#ifdef CONFIG_HPET_TIMER
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static inline int hpet_dev_id(struct irq_domain *domain)
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{
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struct msi_domain_info *info = msi_get_domain_info(domain);
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return (int)(long)info->data;
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}
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static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
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{
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hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
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}
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static struct irq_chip hpet_msi_controller __ro_after_init = {
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.name = "HPET-MSI",
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.irq_unmask = hpet_msi_unmask,
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.irq_mask = hpet_msi_mask,
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.irq_ack = irq_chip_ack_parent,
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.irq_set_affinity = msi_domain_set_affinity,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_compose_msi_msg = irq_msi_compose_msg,
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.irq_write_msi_msg = hpet_msi_write_msg,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
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msi_alloc_info_t *arg)
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{
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return arg->hpet_index;
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}
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static int hpet_msi_init(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq,
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irq_hw_number_t hwirq, msi_alloc_info_t *arg)
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{
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
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handle_edge_irq, arg->hpet_data, "edge");
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return 0;
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}
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static void hpet_msi_free(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq)
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{
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irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
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}
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static struct msi_domain_ops hpet_msi_domain_ops = {
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.get_hwirq = hpet_msi_get_hwirq,
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.msi_init = hpet_msi_init,
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.msi_free = hpet_msi_free,
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};
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static struct msi_domain_info hpet_msi_domain_info = {
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.ops = &hpet_msi_domain_ops,
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.chip = &hpet_msi_controller,
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};
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struct irq_domain *hpet_create_irq_domain(int hpet_id)
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|
{
|
|
struct msi_domain_info *domain_info;
|
|
struct irq_domain *parent, *d;
|
|
struct irq_alloc_info info;
|
|
struct fwnode_handle *fn;
|
|
|
|
if (x86_vector_domain == NULL)
|
|
return NULL;
|
|
|
|
domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
|
|
if (!domain_info)
|
|
return NULL;
|
|
|
|
*domain_info = hpet_msi_domain_info;
|
|
domain_info->data = (void *)(long)hpet_id;
|
|
|
|
init_irq_alloc_info(&info, NULL);
|
|
info.type = X86_IRQ_ALLOC_TYPE_HPET;
|
|
info.hpet_id = hpet_id;
|
|
parent = irq_remapping_get_ir_irq_domain(&info);
|
|
if (parent == NULL)
|
|
parent = x86_vector_domain;
|
|
else
|
|
hpet_msi_controller.name = "IR-HPET-MSI";
|
|
|
|
fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
|
|
hpet_id);
|
|
if (!fn) {
|
|
kfree(domain_info);
|
|
return NULL;
|
|
}
|
|
|
|
d = msi_create_irq_domain(fn, domain_info, parent);
|
|
irq_domain_free_fwnode(fn);
|
|
return d;
|
|
}
|
|
|
|
int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc,
|
|
int dev_num)
|
|
{
|
|
struct irq_alloc_info info;
|
|
|
|
init_irq_alloc_info(&info, NULL);
|
|
info.type = X86_IRQ_ALLOC_TYPE_HPET;
|
|
info.hpet_data = hc;
|
|
info.hpet_id = hpet_dev_id(domain);
|
|
info.hpet_index = dev_num;
|
|
|
|
return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
|
|
}
|
|
#endif
|