mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
13da9e200f
This reverts commitb3b77c8cae, which was also totally broken (see commit0d2daf5cc8that reverted the crc32 version of it). As reported by Stephen Rothwell, it causes problems on big-endian machines: > In file included from fs/jfs/jfs_types.h:33, > from fs/jfs/jfs_incore.h:26, > from fs/jfs/file.c:22: > fs/jfs/endian24.h:36:101: warning: "__LITTLE_ENDIAN" is not defined The kernel has never had that crazy "__BYTE_ORDER == __LITTLE_ENDIAN" model. It's not how we do things, and it isn't how we _should_ do things. So don't go there. Requested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
116 lines
3.7 KiB
C
116 lines
3.7 KiB
C
#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("addcc %r4,%5,%1\n\t" \
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"addx %r2,%3,%0\n" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%rJ" ((USItype)(ah)), \
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"rI" ((USItype)(bh)), \
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"%rJ" ((USItype)(al)), \
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"rI" ((USItype)(bl)) \
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: "cc")
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("subcc %r4,%5,%1\n\t" \
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"subx %r2,%3,%0\n" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "rJ" ((USItype)(ah)), \
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"rI" ((USItype)(bh)), \
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"rJ" ((USItype)(al)), \
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"rI" ((USItype)(bl)) \
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: "cc")
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("! Inlined umul_ppmm\n\t" \
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"wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n\t" \
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"sra %3,31,%%g2 ! Don't move this insn\n\t" \
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"and %2,%%g2,%%g2 ! Don't move this insn\n\t" \
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"andcc %%g0,0,%%g1 ! Don't move this insn\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,%3,%%g1\n\t" \
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"mulscc %%g1,0,%%g1\n\t" \
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"add %%g1,%%g2,%0\n\t" \
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"rd %%y,%1\n" \
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: "=r" ((USItype)(w1)), \
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"=r" ((USItype)(w0)) \
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: "%rI" ((USItype)(u)), \
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"r" ((USItype)(v)) \
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: "%g1", "%g2", "cc")
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/* It's quite necessary to add this much assembler for the sparc.
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The default udiv_qrnnd (in C) is more than 10 times slower! */
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#define udiv_qrnnd(q, r, n1, n0, d) \
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__asm__ ("! Inlined udiv_qrnnd\n\t" \
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"mov 32,%%g1\n\t" \
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"subcc %1,%2,%%g0\n\t" \
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"1: bcs 5f\n\t" \
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"addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
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"sub %1,%2,%1 ! this kills msb of n\n\t" \
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"addx %1,%1,%1 ! so this can't give carry\n\t" \
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"subcc %%g1,1,%%g1\n\t" \
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"2: bne 1b\n\t" \
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"subcc %1,%2,%%g0\n\t" \
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"bcs 3f\n\t" \
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"addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
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"b 3f\n\t" \
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"sub %1,%2,%1 ! this kills msb of n\n\t" \
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"4: sub %1,%2,%1\n\t" \
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"5: addxcc %1,%1,%1\n\t" \
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"bcc 2b\n\t" \
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"subcc %%g1,1,%%g1\n\t" \
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"! Got carry from n. Subtract next step to cancel this carry.\n\t" \
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"bne 4b\n\t" \
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"addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n\t" \
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"sub %1,%2,%1\n\t" \
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"3: xnor %0,0,%0\n\t" \
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"! End of inline udiv_qrnnd\n" \
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: "=&r" ((USItype)(q)), \
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"=&r" ((USItype)(r)) \
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: "r" ((USItype)(d)), \
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"1" ((USItype)(n1)), \
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"0" ((USItype)(n0)) : "%g1", "cc")
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#define UDIV_NEEDS_NORMALIZATION 0
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#define abort() \
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return 0
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#ifdef __BIG_ENDIAN
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#define __BYTE_ORDER __BIG_ENDIAN
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#else
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#define __BYTE_ORDER __LITTLE_ENDIAN
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#endif
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