mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 21:15:11 +07:00
621ecd8d21
In contrast to GICv2 SGIs in a GICv3 implementation are not triggered by a MMIO write, but with a system register write. KVM knows about that register already, we just need to implement the handler and wire it up to the core KVM/ARM code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* VGICv3 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_emulate.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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/* extract @num bytes at @offset bytes offset in data */
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static unsigned long extract_bytes(unsigned long data, unsigned int offset,
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unsigned int num)
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{
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return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
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}
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static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 value = 0;
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switch (addr & 0x0c) {
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case GICD_CTLR:
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if (vcpu->kvm->arch.vgic.enabled)
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value |= GICD_CTLR_ENABLE_SS_G1;
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value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
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break;
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case GICD_TYPER:
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value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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value = (value >> 5) - 1;
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value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
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break;
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case GICD_IIDR:
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value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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break;
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default:
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return 0;
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}
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return value;
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}
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static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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bool was_enabled = dist->enabled;
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switch (addr & 0x0c) {
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case GICD_CTLR:
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dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
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if (!was_enabled && dist->enabled)
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vgic_kick_vcpus(vcpu->kvm);
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break;
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case GICD_TYPER:
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case GICD_IIDR:
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return;
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}
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}
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static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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int intid = VGIC_ADDR_TO_INTID(addr, 64);
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
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if (!irq)
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return 0;
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/* The upper word is RAZ for us. */
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if (addr & 4)
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return 0;
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return extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
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}
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static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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int intid = VGIC_ADDR_TO_INTID(addr, 64);
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
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if (!irq)
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return;
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/* The upper word is WI for us since we don't implement Aff3. */
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if (addr & 4)
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return;
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spin_lock(&irq->irq_lock);
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/* We only care about and preserve Aff0, Aff1 and Aff2. */
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irq->mpidr = val & GENMASK(23, 0);
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irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
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spin_unlock(&irq->irq_lock);
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}
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static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
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int target_vcpu_id = vcpu->vcpu_id;
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u64 value;
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value = (mpidr & GENMASK(23, 0)) << 32;
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value |= ((target_vcpu_id & 0xffff) << 8);
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if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
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value |= GICR_TYPER_LAST;
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return extract_bytes(value, addr & 7, len);
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}
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static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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}
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static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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switch (addr & 0xffff) {
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case GICD_PIDR2:
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/* report a GICv3 compliant implementation */
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return 0x3b;
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}
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return 0;
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}
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/*
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* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
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* redistributors, while SPIs are covered by registers in the distributor
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* block. Trying to set private IRQs in this block gets ignored.
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* We take some special care here to fix the calculation of the register
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* offset.
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*/
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#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = bpi, \
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.len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
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.access_flags = acc, \
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.read = vgic_mmio_read_raz, \
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.write = vgic_mmio_write_wi, \
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}, { \
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.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
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.bits_per_irq = bpi, \
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.len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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static const struct vgic_register_region vgic_v3_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
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vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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vgic_mmio_read_config, vgic_mmio_write_config, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
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vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
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vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
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VGIC_ACCESS_32bit),
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};
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static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
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vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
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vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
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vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
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VGIC_ACCESS_32bit),
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};
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static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
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vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
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vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
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vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
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vgic_mmio_read_config, vgic_mmio_write_config, 8,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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};
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v3_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_64K;
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}
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int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
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{
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int nr_vcpus = atomic_read(&kvm->online_vcpus);
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struct kvm_vcpu *vcpu;
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struct vgic_io_device *devices;
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int c, ret = 0;
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devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
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GFP_KERNEL);
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if (!devices)
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return -ENOMEM;
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kvm_for_each_vcpu(c, vcpu, kvm) {
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gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
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gpa_t sgi_base = rd_base + SZ_64K;
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struct vgic_io_device *rd_dev = &devices[c * 2];
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struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];
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kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
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rd_dev->base_addr = rd_base;
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rd_dev->regions = vgic_v3_rdbase_registers;
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rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
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rd_dev->redist_vcpu = vcpu;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
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SZ_64K, &rd_dev->dev);
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mutex_unlock(&kvm->slots_lock);
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if (ret)
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break;
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kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
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sgi_dev->base_addr = sgi_base;
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sgi_dev->regions = vgic_v3_sgibase_registers;
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sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
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sgi_dev->redist_vcpu = vcpu;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
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SZ_64K, &sgi_dev->dev);
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mutex_unlock(&kvm->slots_lock);
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if (ret) {
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&rd_dev->dev);
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break;
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}
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}
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if (ret) {
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/* The current c failed, so we start with the previous one. */
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for (c--; c >= 0; c--) {
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&devices[c * 2].dev);
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
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&devices[c * 2 + 1].dev);
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}
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kfree(devices);
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} else {
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kvm->arch.vgic.redist_iodevs = devices;
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}
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return ret;
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}
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/*
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* Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
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* generation register ICC_SGI1R_EL1) with a given VCPU.
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* If the VCPU's MPIDR matches, return the level0 affinity, otherwise
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* return -1.
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*/
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static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
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{
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unsigned long affinity;
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int level0;
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/*
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* Split the current VCPU's MPIDR into affinity level 0 and the
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* rest as this is what we have to compare against.
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*/
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affinity = kvm_vcpu_get_mpidr_aff(vcpu);
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level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
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affinity &= ~MPIDR_LEVEL_MASK;
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/* bail out if the upper three levels don't match */
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if (sgi_aff != affinity)
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return -1;
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/* Is this VCPU's bit set in the mask ? */
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if (!(sgi_cpu_mask & BIT(level0)))
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return -1;
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return level0;
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}
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/*
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* The ICC_SGI* registers encode the affinity differently from the MPIDR,
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* so provide a wrapper to use the existing defines to isolate a certain
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* affinity level.
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*/
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#define SGI_AFFINITY_LEVEL(reg, level) \
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((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
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>> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
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/**
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* vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
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* @vcpu: The VCPU requesting a SGI
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* @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
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*
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* With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
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* This will trap in sys_regs.c and call this function.
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* This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
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* target processors as well as a bitmask of 16 Aff0 CPUs.
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* If the interrupt routing mode bit is not set, we iterate over all VCPUs to
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* check for matching ones. If this bit is set, we signal all, but not the
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* calling VCPU.
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*/
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void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
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{
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struct kvm *kvm = vcpu->kvm;
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struct kvm_vcpu *c_vcpu;
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u16 target_cpus;
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u64 mpidr;
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int sgi, c;
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int vcpu_id = vcpu->vcpu_id;
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bool broadcast;
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sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
|
|
broadcast = reg & BIT(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
|
|
target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
|
|
mpidr = SGI_AFFINITY_LEVEL(reg, 3);
|
|
mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
|
|
mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
|
|
|
|
/*
|
|
* We iterate over all VCPUs to find the MPIDRs matching the request.
|
|
* If we have handled one CPU, we clear its bit to detect early
|
|
* if we are already finished. This avoids iterating through all
|
|
* VCPUs when most of the times we just signal a single VCPU.
|
|
*/
|
|
kvm_for_each_vcpu(c, c_vcpu, kvm) {
|
|
struct vgic_irq *irq;
|
|
|
|
/* Exit early if we have dealt with all requested CPUs */
|
|
if (!broadcast && target_cpus == 0)
|
|
break;
|
|
|
|
/* Don't signal the calling VCPU */
|
|
if (broadcast && c == vcpu_id)
|
|
continue;
|
|
|
|
if (!broadcast) {
|
|
int level0;
|
|
|
|
level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
|
|
if (level0 == -1)
|
|
continue;
|
|
|
|
/* remove this matching VCPU from the mask */
|
|
target_cpus &= ~BIT(level0);
|
|
}
|
|
|
|
irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
|
|
|
|
spin_lock(&irq->irq_lock);
|
|
irq->pending = true;
|
|
|
|
vgic_queue_irq_unlock(vcpu->kvm, irq);
|
|
}
|
|
}
|