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9d44dcb908
PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we access other FIA registers. In Tiger Lake we have multiple/modular FIAs so it makes sense to start moving all access to their registers to a common place. While at it, make it clear that we will only ever call this function for ports with TC phy. Previously we were relying on tc_mode being TC_PORT_TBT_ALT for combo phy ports. However it's confusing since in this same function we have checks for is_tc_port. Also, if we manage to make each phy access only their own field, we may in future add them as a union inside intel_digital_port. v2: Fix coding style while moving the code Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190708172815.6814-4-lucas.demarchi@intel.com
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_TC_H__
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#define __INTEL_TC_H__
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include "intel_drv.h"
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bool intel_tc_port_connected(struct intel_digital_port *dig_port);
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u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
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int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
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void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
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int required_lanes);
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void intel_tc_port_sanitize(struct intel_digital_port *dig_port);
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void intel_tc_port_lock(struct intel_digital_port *dig_port);
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void intel_tc_port_unlock(struct intel_digital_port *dig_port);
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void intel_tc_port_get_link(struct intel_digital_port *dig_port,
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int required_lanes);
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void intel_tc_port_put_link(struct intel_digital_port *dig_port);
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static inline int intel_tc_port_ref_held(struct intel_digital_port *dig_port)
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{
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return mutex_is_locked(&dig_port->tc_lock) ||
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dig_port->tc_link_refcount;
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}
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void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
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#endif /* __INTEL_TC_H__ */
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