mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:26:42 +07:00
d7b41b1fdf
We shouldn't directly access sysdata to get the device node. We should be calling pci_device_to_OF_node(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
920 lines
22 KiB
C
920 lines
22 KiB
C
/*
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* Copyright (C) 2001 Allan Trautman, IBM Corporation
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* Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp
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*
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* iSeries specific routines for PCI.
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*
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* Based on code from pci.c and iSeries_pci.c 32bit
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#undef DEBUG
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/iommu.h>
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#include <asm/abs_addr.h>
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#include <asm/firmware.h>
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#include <asm/iseries/hv_types.h>
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#include <asm/iseries/hv_call_xm.h>
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#include <asm/iseries/mf.h>
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#include <asm/iseries/iommu.h>
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#include <asm/ppc-pci.h>
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#include "irq.h"
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#include "pci.h"
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#include "call_pci.h"
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#define PCI_RETRY_MAX 3
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static int limit_pci_retries = 1; /* Set Retry Error on. */
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/*
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* Table defines
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* Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
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*/
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#define IOMM_TABLE_MAX_ENTRIES 1024
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#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
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#define BASE_IO_MEMORY 0xE000000000000000UL
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#define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL
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static unsigned long max_io_memory = BASE_IO_MEMORY;
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static long current_iomm_table_entry;
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/*
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* Lookup Tables.
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*/
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static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
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static u64 ds_addr_table[IOMM_TABLE_MAX_ENTRIES];
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static DEFINE_SPINLOCK(iomm_table_lock);
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/*
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* Generate a Direct Select Address for the Hypervisor
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*/
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static inline u64 iseries_ds_addr(struct device_node *node)
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{
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struct pci_dn *pdn = PCI_DN(node);
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const u32 *sbp = of_get_property(node, "linux,subbus", NULL);
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return ((u64)pdn->busno << 48) + ((u64)(sbp ? *sbp : 0) << 40)
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+ ((u64)0x10 << 32);
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}
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/*
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* Size of Bus VPD data
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*/
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#define BUS_VPDSIZE 1024
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/*
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* Bus Vpd Tags
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*/
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#define VPD_END_OF_AREA 0x79
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#define VPD_ID_STRING 0x82
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#define VPD_VENDOR_AREA 0x84
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/*
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* Mfg Area Tags
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*/
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#define VPD_FRU_FRAME_ID 0x4649 /* "FI" */
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#define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */
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#define VPD_SLOT_MAP 0x534D /* "SM" */
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/*
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* Structures of the areas
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*/
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struct mfg_vpd_area {
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u16 tag;
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u8 length;
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u8 data1;
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u8 data2;
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};
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#define MFG_ENTRY_SIZE 3
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struct slot_map {
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u8 agent;
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u8 secondary_agent;
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u8 phb;
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char card_location[3];
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char parms[8];
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char reserved[2];
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};
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#define SLOT_ENTRY_SIZE 16
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/*
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* Parse the Slot Area
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*/
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static void __init iseries_parse_slot_area(struct slot_map *map, int len,
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HvAgentId agent, u8 *phb, char card[4])
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{
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/*
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* Parse Slot label until we find the one requested
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*/
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while (len > 0) {
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if (map->agent == agent) {
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/*
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* If Phb wasn't found, grab the entry first one found.
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*/
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if (*phb == 0xff)
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*phb = map->phb;
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/* Found it, extract the data. */
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if (map->phb == *phb) {
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memcpy(card, &map->card_location, 3);
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card[3] = 0;
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break;
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}
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}
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/* Point to the next Slot */
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map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE);
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len -= SLOT_ENTRY_SIZE;
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}
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}
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/*
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* Parse the Mfg Area
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*/
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static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len,
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HvAgentId agent, u8 *phb, u8 *frame, char card[4])
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{
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u16 slot_map_fmt = 0;
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/* Parse Mfg Data */
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while (len > 0) {
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int mfg_tag_len = area->length;
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/* Frame ID (FI 4649020310 ) */
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if (area->tag == VPD_FRU_FRAME_ID)
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*frame = area->data1;
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/* Slot Map Format (MF 4D46020004 ) */
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else if (area->tag == VPD_SLOT_MAP_FORMAT)
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slot_map_fmt = (area->data1 * 256)
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+ area->data2;
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/* Slot Map (SM 534D90 */
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else if (area->tag == VPD_SLOT_MAP) {
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struct slot_map *slot_map;
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if (slot_map_fmt == 0x1004)
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slot_map = (struct slot_map *)((char *)area
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+ MFG_ENTRY_SIZE + 1);
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else
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slot_map = (struct slot_map *)((char *)area
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+ MFG_ENTRY_SIZE);
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iseries_parse_slot_area(slot_map, mfg_tag_len,
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agent, phb, card);
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}
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/*
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* Point to the next Mfg Area
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* Use defined size, sizeof give wrong answer
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*/
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area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len
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+ MFG_ENTRY_SIZE);
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len -= (mfg_tag_len + MFG_ENTRY_SIZE);
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}
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}
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/*
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* Look for "BUS".. Data is not Null terminated.
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* PHBID of 0xFF indicates PHB was not found in VPD Data.
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*/
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static u8 __init iseries_parse_phbid(u8 *area, int len)
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{
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while (len > 0) {
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if ((*area == 'B') && (*(area + 1) == 'U')
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&& (*(area + 2) == 'S')) {
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area += 3;
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while (*area == ' ')
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area++;
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return *area & 0x0F;
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}
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area++;
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len--;
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}
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return 0xff;
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}
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/*
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* Parse out the VPD Areas
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*/
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static void __init iseries_parse_vpd(u8 *data, int data_len,
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HvAgentId agent, u8 *frame, char card[4])
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{
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u8 phb = 0xff;
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while (data_len > 0) {
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int len;
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u8 tag = *data;
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if (tag == VPD_END_OF_AREA)
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break;
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len = *(data + 1) + (*(data + 2) * 256);
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data += 3;
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data_len -= 3;
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if (tag == VPD_ID_STRING)
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phb = iseries_parse_phbid(data, len);
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else if (tag == VPD_VENDOR_AREA)
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iseries_parse_mfg_area((struct mfg_vpd_area *)data, len,
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agent, &phb, frame, card);
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/* Point to next Area. */
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data += len;
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data_len -= len;
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}
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}
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static int __init iseries_get_location_code(u16 bus, HvAgentId agent,
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u8 *frame, char card[4])
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{
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int status = 0;
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int bus_vpd_len = 0;
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u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL);
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if (bus_vpd == NULL) {
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printk("PCI: Bus VPD Buffer allocation failure.\n");
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return 0;
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}
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bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd),
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BUS_VPDSIZE);
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if (bus_vpd_len == 0) {
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printk("PCI: Bus VPD Buffer zero length.\n");
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goto out_free;
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}
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/* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */
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/* Make sure this is what I think it is */
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if (*bus_vpd != VPD_ID_STRING) {
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printk("PCI: Bus VPD Buffer missing starting tag.\n");
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goto out_free;
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}
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iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card);
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status = 1;
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out_free:
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kfree(bus_vpd);
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return status;
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}
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/*
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* Prints the device information.
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* - Pass in pci_dev* pointer to the device.
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* - Pass in the device count
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*
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* Format:
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* PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet
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* controller
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*/
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static void __init iseries_device_information(struct pci_dev *pdev,
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u16 bus, HvSubBusNumber subbus)
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{
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u8 frame = 0;
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char card[4];
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HvAgentId agent;
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agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus),
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ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus));
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if (iseries_get_location_code(bus, agent, &frame, card)) {
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printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, "
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"Card %4s 0x%04X\n", pci_name(pdev), pdev->vendor,
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frame, card, (int)(pdev->class >> 8));
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}
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}
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/*
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* iomm_table_allocate_entry
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*
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* Adds pci_dev entry in address translation table
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*
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* - Allocates the number of entries required in table base on BAR
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* size.
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* - Allocates starting at BASE_IO_MEMORY and increases.
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* - The size is round up to be a multiple of entry size.
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* - CurrentIndex is incremented to keep track of the last entry.
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* - Builds the resource entry for allocated BARs.
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*/
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static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
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{
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struct resource *bar_res = &dev->resource[bar_num];
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long bar_size = pci_resource_len(dev, bar_num);
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struct device_node *dn = pci_device_to_OF_node(dev);
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/*
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* No space to allocate, quick exit, skip Allocation.
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*/
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if (bar_size == 0)
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return;
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/*
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* Set Resource values.
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*/
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spin_lock(&iomm_table_lock);
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bar_res->start = BASE_IO_MEMORY +
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IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
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bar_res->end = bar_res->start + bar_size - 1;
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/*
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* Allocate the number of table entries needed for BAR.
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*/
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while (bar_size > 0 ) {
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iomm_table[current_iomm_table_entry] = dn;
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ds_addr_table[current_iomm_table_entry] =
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iseries_ds_addr(dn) | (bar_num << 24);
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bar_size -= IOMM_TABLE_ENTRY_SIZE;
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++current_iomm_table_entry;
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}
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max_io_memory = BASE_IO_MEMORY +
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IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
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spin_unlock(&iomm_table_lock);
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}
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/*
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* allocate_device_bars
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*
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* - Allocates ALL pci_dev BAR's and updates the resources with the
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* BAR value. BARS with zero length will have the resources
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* The HvCallPci_getBarParms is used to get the size of the BAR
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* space. It calls iomm_table_allocate_entry to allocate
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* each entry.
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* - Loops through The Bar resources(0 - 5) including the ROM
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* is resource(6).
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*/
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static void __init allocate_device_bars(struct pci_dev *dev)
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{
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int bar_num;
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for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
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iomm_table_allocate_entry(dev, bar_num);
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}
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/*
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* Log error information to system console.
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* Filter out the device not there errors.
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* PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
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* PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
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* PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
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*/
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static void pci_log_error(char *error, int bus, int subbus,
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int agent, int hv_res)
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{
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if (hv_res == 0x0302)
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return;
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printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
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error, bus, subbus, agent, hv_res);
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}
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/*
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* Look down the chain to find the matching Device Device
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*/
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static struct device_node *find_device_node(int bus, int devfn)
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{
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struct device_node *node;
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for (node = NULL; (node = of_find_all_nodes(node)); ) {
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struct pci_dn *pdn = PCI_DN(node);
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if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
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return node;
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}
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return NULL;
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}
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/*
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* iSeries_pcibios_fixup_resources
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*
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* Fixes up all resources for devices
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*/
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void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev)
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{
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const u32 *agent;
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const u32 *sub_bus;
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unsigned char bus = pdev->bus->number;
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struct device_node *node;
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int i;
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node = pci_device_to_OF_node(pdev);
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pr_debug("PCI: iSeries %s, pdev %p, node %p\n",
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pci_name(pdev), pdev, node);
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if (!node) {
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printk("PCI: %s disabled, device tree entry not found !\n",
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pci_name(pdev));
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for (i = 0; i <= PCI_ROM_RESOURCE; i++)
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pdev->resource[i].flags = 0;
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return;
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}
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sub_bus = of_get_property(node, "linux,subbus", NULL);
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agent = of_get_property(node, "linux,agent-id", NULL);
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if (agent && sub_bus) {
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u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus);
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int err;
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err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq);
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if (err)
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pci_log_error("Connect Bus Unit",
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bus, *sub_bus, *agent, err);
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else {
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err = HvCallPci_configStore8(bus, *sub_bus,
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*agent, PCI_INTERRUPT_LINE, irq);
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if (err)
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pci_log_error("PciCfgStore Irq Failed!",
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bus, *sub_bus, *agent, err);
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else
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pdev->irq = irq;
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}
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}
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allocate_device_bars(pdev);
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iseries_device_information(pdev, bus, *sub_bus);
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}
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/*
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* iSeries_pci_final_fixup(void)
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*/
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void __init iSeries_pci_final_fixup(void)
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{
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/* Fix up at the device node and pci_dev relationship */
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mf_display_src(0xC9000100);
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iSeries_activate_IRQs();
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mf_display_src(0xC9000200);
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}
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/*
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* Config space read and write functions.
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* For now at least, we look for the device node for the bus and devfn
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* that we are asked to access. It may be possible to translate the devfn
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* to a subbus and deviceid more directly.
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*/
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static u64 hv_cfg_read_func[4] = {
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HvCallPciConfigLoad8, HvCallPciConfigLoad16,
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HvCallPciConfigLoad32, HvCallPciConfigLoad32
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};
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static u64 hv_cfg_write_func[4] = {
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HvCallPciConfigStore8, HvCallPciConfigStore16,
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HvCallPciConfigStore32, HvCallPciConfigStore32
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};
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/*
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* Read PCI config space
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*/
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static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int size, u32 *val)
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{
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struct device_node *node = find_device_node(bus->number, devfn);
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u64 fn;
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struct HvCallPci_LoadReturn ret;
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if (node == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (offset > 255) {
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*val = ~0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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fn = hv_cfg_read_func[(size - 1) & 3];
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HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
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|
|
if (ret.rc != 0) {
|
|
*val = ~0;
|
|
return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
|
|
}
|
|
|
|
*val = ret.value;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write PCI config space
|
|
*/
|
|
|
|
static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int size, u32 val)
|
|
{
|
|
struct device_node *node = find_device_node(bus->number, devfn);
|
|
u64 fn;
|
|
u64 ret;
|
|
|
|
if (node == NULL)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
if (offset > 255)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
fn = hv_cfg_write_func[(size - 1) & 3];
|
|
ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
|
|
|
|
if (ret != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_ops iSeries_pci_ops = {
|
|
.read = iSeries_pci_read_config,
|
|
.write = iSeries_pci_write_config
|
|
};
|
|
|
|
/*
|
|
* Check Return Code
|
|
* -> On Failure, print and log information.
|
|
* Increment Retry Count, if exceeds max, panic partition.
|
|
*
|
|
* PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
|
|
* PCI: Device 23.90 ReadL Retry( 1)
|
|
* PCI: Device 23.90 ReadL Retry Successful(1)
|
|
*/
|
|
static int check_return_code(char *type, struct device_node *dn,
|
|
int *retry, u64 ret)
|
|
{
|
|
if (ret != 0) {
|
|
struct pci_dn *pdn = PCI_DN(dn);
|
|
|
|
(*retry)++;
|
|
printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
|
|
type, pdn->busno, pdn->devfn,
|
|
*retry, (int)ret);
|
|
/*
|
|
* Bump the retry and check for retry count exceeded.
|
|
* If, Exceeded, panic the system.
|
|
*/
|
|
if (((*retry) > PCI_RETRY_MAX) &&
|
|
(limit_pci_retries > 0)) {
|
|
mf_display_src(0xB6000103);
|
|
panic_timeout = 0;
|
|
panic("PCI: Hardware I/O Error, SRC B6000103, "
|
|
"Automatic Reboot Disabled.\n");
|
|
}
|
|
return -1; /* Retry Try */
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Translate the I/O Address into a device node, bar, and bar offset.
|
|
* Note: Make sure the passed variable end up on the stack to avoid
|
|
* the exposure of being device global.
|
|
*/
|
|
static inline struct device_node *xlate_iomm_address(
|
|
const volatile void __iomem *addr,
|
|
u64 *dsaptr, u64 *bar_offset, const char *func)
|
|
{
|
|
unsigned long orig_addr;
|
|
unsigned long base_addr;
|
|
unsigned long ind;
|
|
struct device_node *dn;
|
|
|
|
orig_addr = (unsigned long __force)addr;
|
|
if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if (time_after(jiffies, last_jiffies + 60 * HZ)) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR
|
|
"iSeries_%s: invalid access at IO address %p\n",
|
|
func, addr);
|
|
return NULL;
|
|
}
|
|
base_addr = orig_addr - BASE_IO_MEMORY;
|
|
ind = base_addr / IOMM_TABLE_ENTRY_SIZE;
|
|
dn = iomm_table[ind];
|
|
|
|
if (dn != NULL) {
|
|
*dsaptr = ds_addr_table[ind];
|
|
*bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE;
|
|
} else
|
|
panic("PCI: Invalid PCI IO address detected!\n");
|
|
return dn;
|
|
}
|
|
|
|
/*
|
|
* Read MM I/O Instructions for the iSeries
|
|
* On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
|
|
* else, data is returned in Big Endian format.
|
|
*/
|
|
static u8 iseries_readb(const volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte");
|
|
|
|
if (dn == NULL)
|
|
return 0xff;
|
|
do {
|
|
HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0);
|
|
} while (check_return_code("RDB", dn, &retry, ret.rc) != 0);
|
|
|
|
return ret.value;
|
|
}
|
|
|
|
static u16 iseries_readw_be(const volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "read_word");
|
|
|
|
if (dn == NULL)
|
|
return 0xffff;
|
|
do {
|
|
HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
|
|
bar_offset, 0);
|
|
} while (check_return_code("RDW", dn, &retry, ret.rc) != 0);
|
|
|
|
return ret.value;
|
|
}
|
|
|
|
static u32 iseries_readl_be(const volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "read_long");
|
|
|
|
if (dn == NULL)
|
|
return 0xffffffff;
|
|
do {
|
|
HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
|
|
bar_offset, 0);
|
|
} while (check_return_code("RDL", dn, &retry, ret.rc) != 0);
|
|
|
|
return ret.value;
|
|
}
|
|
|
|
/*
|
|
* Write MM I/O Instructions for the iSeries
|
|
*
|
|
*/
|
|
static void iseries_writeb(u8 data, volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
u64 rc;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte");
|
|
|
|
if (dn == NULL)
|
|
return;
|
|
do {
|
|
rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0);
|
|
} while (check_return_code("WWB", dn, &retry, rc) != 0);
|
|
}
|
|
|
|
static void iseries_writew_be(u16 data, volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
u64 rc;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "write_word");
|
|
|
|
if (dn == NULL)
|
|
return;
|
|
do {
|
|
rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0);
|
|
} while (check_return_code("WWW", dn, &retry, rc) != 0);
|
|
}
|
|
|
|
static void iseries_writel_be(u32 data, volatile void __iomem *addr)
|
|
{
|
|
u64 bar_offset;
|
|
u64 dsa;
|
|
int retry = 0;
|
|
u64 rc;
|
|
struct device_node *dn =
|
|
xlate_iomm_address(addr, &dsa, &bar_offset, "write_long");
|
|
|
|
if (dn == NULL)
|
|
return;
|
|
do {
|
|
rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0);
|
|
} while (check_return_code("WWL", dn, &retry, rc) != 0);
|
|
}
|
|
|
|
static u16 iseries_readw(const volatile void __iomem *addr)
|
|
{
|
|
return le16_to_cpu(iseries_readw_be(addr));
|
|
}
|
|
|
|
static u32 iseries_readl(const volatile void __iomem *addr)
|
|
{
|
|
return le32_to_cpu(iseries_readl_be(addr));
|
|
}
|
|
|
|
static void iseries_writew(u16 data, volatile void __iomem *addr)
|
|
{
|
|
iseries_writew_be(cpu_to_le16(data), addr);
|
|
}
|
|
|
|
static void iseries_writel(u32 data, volatile void __iomem *addr)
|
|
{
|
|
iseries_writel(cpu_to_le32(data), addr);
|
|
}
|
|
|
|
static void iseries_readsb(const volatile void __iomem *addr, void *buf,
|
|
unsigned long count)
|
|
{
|
|
u8 *dst = buf;
|
|
while(count-- > 0)
|
|
*(dst++) = iseries_readb(addr);
|
|
}
|
|
|
|
static void iseries_readsw(const volatile void __iomem *addr, void *buf,
|
|
unsigned long count)
|
|
{
|
|
u16 *dst = buf;
|
|
while(count-- > 0)
|
|
*(dst++) = iseries_readw_be(addr);
|
|
}
|
|
|
|
static void iseries_readsl(const volatile void __iomem *addr, void *buf,
|
|
unsigned long count)
|
|
{
|
|
u32 *dst = buf;
|
|
while(count-- > 0)
|
|
*(dst++) = iseries_readl_be(addr);
|
|
}
|
|
|
|
static void iseries_writesb(volatile void __iomem *addr, const void *buf,
|
|
unsigned long count)
|
|
{
|
|
const u8 *src = buf;
|
|
while(count-- > 0)
|
|
iseries_writeb(*(src++), addr);
|
|
}
|
|
|
|
static void iseries_writesw(volatile void __iomem *addr, const void *buf,
|
|
unsigned long count)
|
|
{
|
|
const u16 *src = buf;
|
|
while(count-- > 0)
|
|
iseries_writew_be(*(src++), addr);
|
|
}
|
|
|
|
static void iseries_writesl(volatile void __iomem *addr, const void *buf,
|
|
unsigned long count)
|
|
{
|
|
const u32 *src = buf;
|
|
while(count-- > 0)
|
|
iseries_writel_be(*(src++), addr);
|
|
}
|
|
|
|
static void iseries_memset_io(volatile void __iomem *addr, int c,
|
|
unsigned long n)
|
|
{
|
|
volatile char __iomem *d = addr;
|
|
|
|
while (n-- > 0)
|
|
iseries_writeb(c, d++);
|
|
}
|
|
|
|
static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src,
|
|
unsigned long n)
|
|
{
|
|
char *d = dest;
|
|
const volatile char __iomem *s = src;
|
|
|
|
while (n-- > 0)
|
|
*d++ = iseries_readb(s++);
|
|
}
|
|
|
|
static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src,
|
|
unsigned long n)
|
|
{
|
|
const char *s = src;
|
|
volatile char __iomem *d = dest;
|
|
|
|
while (n-- > 0)
|
|
iseries_writeb(*s++, d++);
|
|
}
|
|
|
|
/* We only set MMIO ops. The default PIO ops will be default
|
|
* to the MMIO ops + pci_io_base which is 0 on iSeries as
|
|
* expected so both should work.
|
|
*
|
|
* Note that we don't implement the readq/writeq versions as
|
|
* I don't know of an HV call for doing so. Thus, the default
|
|
* operation will be used instead, which will fault a the value
|
|
* return by iSeries for MMIO addresses always hits a non mapped
|
|
* area. This is as good as the BUG() we used to have there.
|
|
*/
|
|
static struct ppc_pci_io __initdata iseries_pci_io = {
|
|
.readb = iseries_readb,
|
|
.readw = iseries_readw,
|
|
.readl = iseries_readl,
|
|
.readw_be = iseries_readw_be,
|
|
.readl_be = iseries_readl_be,
|
|
.writeb = iseries_writeb,
|
|
.writew = iseries_writew,
|
|
.writel = iseries_writel,
|
|
.writew_be = iseries_writew_be,
|
|
.writel_be = iseries_writel_be,
|
|
.readsb = iseries_readsb,
|
|
.readsw = iseries_readsw,
|
|
.readsl = iseries_readsl,
|
|
.writesb = iseries_writesb,
|
|
.writesw = iseries_writesw,
|
|
.writesl = iseries_writesl,
|
|
.memset_io = iseries_memset_io,
|
|
.memcpy_fromio = iseries_memcpy_fromio,
|
|
.memcpy_toio = iseries_memcpy_toio,
|
|
};
|
|
|
|
/*
|
|
* iSeries_pcibios_init
|
|
*
|
|
* Description:
|
|
* This function checks for all possible system PCI host bridges that connect
|
|
* PCI buses. The system hypervisor is queried as to the guest partition
|
|
* ownership status. A pci_controller is built for any bus which is partially
|
|
* owned or fully owned by this guest partition.
|
|
*/
|
|
void __init iSeries_pcibios_init(void)
|
|
{
|
|
struct pci_controller *phb;
|
|
struct device_node *root = of_find_node_by_path("/");
|
|
struct device_node *node = NULL;
|
|
|
|
/* Install IO hooks */
|
|
ppc_pci_io = iseries_pci_io;
|
|
|
|
pci_probe_only = 1;
|
|
|
|
/* iSeries has no IO space in the common sense, it needs to set
|
|
* the IO base to 0
|
|
*/
|
|
pci_io_base = 0;
|
|
|
|
if (root == NULL) {
|
|
printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
|
|
"of device tree\n");
|
|
return;
|
|
}
|
|
while ((node = of_get_next_child(root, node)) != NULL) {
|
|
HvBusNumber bus;
|
|
const u32 *busp;
|
|
|
|
if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
|
|
continue;
|
|
|
|
busp = of_get_property(node, "bus-range", NULL);
|
|
if (busp == NULL)
|
|
continue;
|
|
bus = *busp;
|
|
printk("bus %d appears to exist\n", bus);
|
|
phb = pcibios_alloc_controller(node);
|
|
if (phb == NULL)
|
|
continue;
|
|
/* All legacy iSeries PHBs are in domain zero */
|
|
phb->global_number = 0;
|
|
|
|
phb->first_busno = bus;
|
|
phb->last_busno = bus;
|
|
phb->ops = &iSeries_pci_ops;
|
|
phb->io_base_virt = (void __iomem *)_IO_BASE;
|
|
phb->io_resource.flags = IORESOURCE_IO;
|
|
phb->io_resource.start = BASE_IO_MEMORY;
|
|
phb->io_resource.end = END_IO_MEMORY;
|
|
phb->io_resource.name = "iSeries PCI IO";
|
|
phb->mem_resources[0].flags = IORESOURCE_MEM;
|
|
phb->mem_resources[0].start = BASE_IO_MEMORY;
|
|
phb->mem_resources[0].end = END_IO_MEMORY;
|
|
phb->mem_resources[0].name = "Series PCI MEM";
|
|
}
|
|
|
|
of_node_put(root);
|
|
|
|
pci_devs_phb_init();
|
|
}
|
|
|