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90751f686e
This adds the four video decoder clock trees.
VDEC_1 is split into two paths on Meson8b and Meson8m2:
- input mux called "vdec_1_sel"
- two dividers ("vdec_1_1_div" and "vdec_1_2_div") and gates ("vdec_1_1"
and "vdec_1_2")
- and an output mux (probably glitch-free) called "vdec_1"
On Meson8 the VDEC_1 tree is simpler because there's only one path:
- input mux called "vdec_1_sel"
- divider ("vdec_1_1_div") and gate ("vdec_1_1")
- (the gate is used as output directly, there's no mux)
The VDEC_HCODEC and VDEC_2 clocks are simple composite clocks each
consisting of an input mux, divider and a gate.
The VDEC_HEVC clock seems to have two paths similar to the VDEC_1 clock.
However, the register offsets of the second clock path is not known.
Amlogic's 3.10 kernel (which is used as reference) sets
HHI_VDEC2_CLK_CNTL[31] to 1 before changing the VDEC_HEVC clock and back
to 0 afterwards. For now, leave a TODO comment and only add the first
path.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190324151423.19063-3-martin.blumenstingl@googlemail.com
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| .. | ||
| axg-aoclk.c | ||
| axg-aoclk.h | ||
| axg-audio.c | ||
| axg-audio.h | ||
| axg.c | ||
| axg.h | ||
| clk-dualdiv.c | ||
| clk-dualdiv.h | ||
| clk-input.c | ||
| clk-input.h | ||
| clk-mpll.c | ||
| clk-mpll.h | ||
| clk-phase.c | ||
| clk-phase.h | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| g12a-aoclk.c | ||
| g12a-aoclk.h | ||
| g12a.c | ||
| g12a.h | ||
| gxbb-aoclk.c | ||
| gxbb-aoclk.h | ||
| gxbb.c | ||
| gxbb.h | ||
| Kconfig | ||
| Makefile | ||
| meson8b.c | ||
| meson8b.h | ||
| meson-aoclk.c | ||
| meson-aoclk.h | ||
| meson-eeclk.c | ||
| meson-eeclk.h | ||
| parm.h | ||
| sclk-div.c | ||
| sclk-div.h | ||
| vid-pll-div.c | ||
| vid-pll-div.h | ||