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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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42d279f913
Create a char device region that will allow acquisition of user portals in order to allow applications to submit DMA operations. A char device will be created per work queue that gets exposed. The workqueue type "user" is used to mark a work queue for user char device. For example if the workqueue 0 of DSA device 0 is marked for char device, then a device node of /dev/dsa/wq0.0 will be created. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/157965026985.73301.976523230037106742.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <uapi/linux/idxd.h>
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#include "idxd.h"
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#include "registers.h"
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struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)
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{
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struct idxd_desc *desc;
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int idx;
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struct idxd_device *idxd = wq->idxd;
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if (idxd->state != IDXD_DEV_ENABLED)
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return ERR_PTR(-EIO);
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if (optype == IDXD_OP_BLOCK)
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percpu_down_read(&wq->submit_lock);
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else if (!percpu_down_read_trylock(&wq->submit_lock))
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return ERR_PTR(-EBUSY);
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if (!atomic_add_unless(&wq->dq_count, 1, wq->size)) {
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int rc;
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if (optype == IDXD_OP_NONBLOCK) {
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percpu_up_read(&wq->submit_lock);
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return ERR_PTR(-EAGAIN);
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}
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percpu_up_read(&wq->submit_lock);
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percpu_down_write(&wq->submit_lock);
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rc = wait_event_interruptible(wq->submit_waitq,
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atomic_add_unless(&wq->dq_count,
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1, wq->size) ||
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idxd->state != IDXD_DEV_ENABLED);
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percpu_up_write(&wq->submit_lock);
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if (rc < 0)
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return ERR_PTR(-EINTR);
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if (idxd->state != IDXD_DEV_ENABLED)
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return ERR_PTR(-EIO);
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} else {
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percpu_up_read(&wq->submit_lock);
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}
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idx = sbitmap_get(&wq->sbmap, 0, false);
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if (idx < 0) {
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atomic_dec(&wq->dq_count);
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return ERR_PTR(-EAGAIN);
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}
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desc = wq->descs[idx];
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memset(desc->hw, 0, sizeof(struct dsa_hw_desc));
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memset(desc->completion, 0, sizeof(struct dsa_completion_record));
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return desc;
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}
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void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc)
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{
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atomic_dec(&wq->dq_count);
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sbitmap_clear_bit(&wq->sbmap, desc->id);
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wake_up(&wq->submit_waitq);
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}
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int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
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{
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struct idxd_device *idxd = wq->idxd;
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int vec = desc->hw->int_handle;
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void __iomem *portal;
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if (idxd->state != IDXD_DEV_ENABLED)
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return -EIO;
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portal = wq->dportal + idxd_get_wq_portal_offset(IDXD_PORTAL_UNLIMITED);
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/*
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* The wmb() flushes writes to coherent DMA data before possibly
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* triggering a DMA read. The wmb() is necessary even on UP because
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* the recipient is a device.
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*/
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wmb();
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iosubmit_cmds512(portal, desc->hw, 1);
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/*
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* Pending the descriptor to the lockless list for the irq_entry
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* that we designated the descriptor to.
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*/
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if (desc->hw->flags & IDXD_OP_FLAG_RCI)
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llist_add(&desc->llnode,
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&idxd->irq_entries[vec].pending_llist);
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return 0;
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}
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