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7d3c425fef
This has grown to be a sizable amount of code, so move it to its own file before we try to refactor anything. For the moment, we are leaving behind the WA BB code and the WAs that get applied (incorrectly) in init_clock_gating, but we will deal with it later. v2: Use intel_ prefix for code that deals with the hardware (Chris) v3: Rebased v4: - Rebased - New license header v5: - Rebased - Added some organisational notes to the file (Chris) v6: Include DOC section in the documentation build (Jani) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [ickle: appease checkpatch, mostly] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/1523376767-18480-1-git-send-email-oscar.mateo@intel.com
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===========================
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drm/i915 Intel GFX Driver
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===========================
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The drm/i915 driver supports all (with the exception of some very early
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models) integrated GFX chipsets with both Intel display and rendering
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blocks. This excludes a set of SoC platforms with an SGX rendering unit,
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those have basic support through the gma500 drm driver.
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Core Driver Infrastructure
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==========================
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This section covers core driver infrastructure used by both the display
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and the GEM parts of the driver.
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Runtime Power Management
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------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
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:doc: runtime pm
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.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
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:internal:
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Interrupt Handling
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------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
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:doc: interrupt handling
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.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
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:functions: intel_irq_init intel_irq_init_hw intel_hpd_init
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.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
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:functions: intel_runtime_pm_disable_interrupts
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.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
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:functions: intel_runtime_pm_enable_interrupts
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Intel GVT-g Guest Support(vGPU)
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-------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
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:doc: Intel GVT-g guest support
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.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
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:internal:
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Intel GVT-g Host Support(vGPU device model)
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-------------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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:doc: Intel GVT-g host support
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.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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:internal:
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Workarounds
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-----------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_workarounds.c
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:doc: Hardware workarounds
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Display Hardware Handling
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=========================
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This section covers everything related to the display hardware including
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the mode setting infrastructure, plane, sprite and cursor handling and
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display, output probing and related topics.
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Mode Setting Infrastructure
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---------------------------
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The i915 driver is thus far the only DRM driver which doesn't use the
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common DRM helper code to implement mode setting sequences. Thus it has
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its own tailor-made infrastructure for executing a display configuration
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change.
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Frontbuffer Tracking
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--------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c
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:doc: frontbuffer tracking
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.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.h
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c
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:functions: i915_gem_track_fb
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Display FIFO Underrun Reporting
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-------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c
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:doc: fifo underrun handling
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.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c
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:internal:
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Plane Configuration
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-------------------
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This section covers plane configuration and composition with the primary
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plane, sprites, cursors and overlays. This includes the infrastructure
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to do atomic vsync'ed updates of all this state and also tightly coupled
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topics like watermark setup and computation, framebuffer compression and
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panel self refresh.
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Atomic Plane Helpers
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--------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c
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:doc: atomic plane helpers
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.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c
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:internal:
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Output Probing
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--------------
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This section covers output probing and related infrastructure like the
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hotplug interrupt storm detection and mitigation code. Note that the
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i915 driver still uses most of the common DRM helper code for output
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probing, so those sections fully apply.
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Hotplug
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-------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c
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:doc: Hotplug
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.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c
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:internal:
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High Definition Audio
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---------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
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:doc: High Definition Audio over HDMI and Display Port
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.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
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:internal:
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.. kernel-doc:: include/drm/i915_component.h
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:internal:
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Intel HDMI LPE Audio Support
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----------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_lpe_audio.c
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:doc: LPE Audio integration for HDMI or DP playback
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.. kernel-doc:: drivers/gpu/drm/i915/intel_lpe_audio.c
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:internal:
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Panel Self Refresh PSR (PSR/SRD)
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--------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c
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:doc: Panel Self Refresh (PSR/SRD)
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.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c
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:internal:
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Frame Buffer Compression (FBC)
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------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c
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:doc: Frame Buffer Compression (FBC)
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.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c
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:internal:
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Display Refresh Rate Switching (DRRS)
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-------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:doc: Display Refresh Rate Switching (DRRS)
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_dp_set_drrs_state
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_edp_drrs_enable
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_edp_drrs_disable
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_edp_drrs_invalidate
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_edp_drrs_flush
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
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:functions: intel_dp_drrs_init
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DPIO
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----
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dpio_phy.c
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:doc: DPIO
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CSR firmware support for DMC
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----------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
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:doc: csr support for dmc
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.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
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:internal:
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Video BIOS Table (VBT)
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----------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c
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:doc: Video BIOS Table (VBT)
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.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/intel_vbt_defs.h
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:internal:
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Display clocks
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--------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_cdclk.c
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:doc: CDCLK / RAWCLK
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.. kernel-doc:: drivers/gpu/drm/i915/intel_cdclk.c
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:internal:
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Display PLLs
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------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.c
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:doc: Display PLLs
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/intel_dpll_mgr.h
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:internal:
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Memory Management and Command Submission
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========================================
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This sections covers all things related to the GEM implementation in the
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i915 driver.
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Intel GPU Basics
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----------------
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An Intel GPU has multiple engines. There are several engine types.
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- RCS engine is for rendering 3D and performing compute, this is named
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`I915_EXEC_RENDER` in user space.
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- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
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space.
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- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
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in user space
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- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
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space.
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- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
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instead it is to be used by user space to specify a default rendering
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engine (for 3D) that may or may not be the same as RCS.
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The Intel GPU family is a family of integrated GPU's using Unified
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Memory Access. For having the GPU "do work", user space will feed the
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GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
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or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
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instruct the GPU to perform work (for example rendering) and that work
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needs memory from which to read and memory to which to write. All memory
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is encapsulated within GEM buffer objects (usually created with the ioctl
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`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
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to create will also list all GEM buffer objects that the batchbuffer reads
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and/or writes. For implementation details of memory management see
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`GEM BO Management Implementation Details`_.
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The i915 driver allows user space to create a context via the ioctl
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`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
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integer. Such a context should be viewed by user-space as -loosely-
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analogous to the idea of a CPU process of an operating system. The i915
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driver guarantees that commands issued to a fixed context are to be
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executed so that writes of a previously issued command are seen by
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reads of following commands. Actions issued between different contexts
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(even if from the same file descriptor) are NOT given that guarantee
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and the only way to synchronize across contexts (even from the same
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file descriptor) is through the use of fences. At least as far back as
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Gen4, also have that a context carries with it a GPU HW context;
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the HW context is essentially (most of atleast) the state of a GPU.
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In addition to the ordering guarantees, the kernel will restore GPU
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state via HW context when commands are issued to a context, this saves
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user space the need to restore (most of atleast) the GPU state at the
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start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
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work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
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to identify what context to use with the command.
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The GPU has its own memory management and address space. The kernel
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driver maintains the memory translation table for the GPU. For older
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GPUs (i.e. those before Gen8), there is a single global such translation
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table, a global Graphics Translation Table (GTT). For newer generation
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GPUs each context has its own translation table, called Per-Process
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Graphics Translation Table (PPGTT). Of important note, is that although
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PPGTT is named per-process it is actually per context. When user space
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submits a batchbuffer, the kernel walks the list of GEM buffer objects
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used by the batchbuffer and guarantees that not only is the memory of
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each such GEM buffer object resident but it is also present in the
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(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
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then it is given an address. Two consequences of this are: the kernel
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needs to edit the batchbuffer submitted to write the correct value of
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the GPU address when a GEM BO is assigned a GPU address and the kernel
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might evict a different GEM BO from the (PP)GTT to make address room
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for another GEM BO. Consequently, the ioctls submitting a batchbuffer
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for execution also include a list of all locations within buffers that
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refer to GPU-addresses so that the kernel can edit the buffer correctly.
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This process is dubbed relocation.
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GEM BO Management Implementation Details
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----------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
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:doc: Virtual Memory Address
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Buffer Object Eviction
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----------------------
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This section documents the interface functions for evicting buffer
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objects to make space available in the virtual gpu address spaces. Note
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that this is mostly orthogonal to shrinking buffer objects caches, which
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has the goal to make main memory (shared with the gpu through the
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unified memory architecture) available.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
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:internal:
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Buffer Object Memory Shrinking
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------------------------------
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This section documents the interface function for shrinking memory usage
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of buffer object caches. Shrinking is used to make main memory
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available. Note that this is mostly orthogonal to evicting buffer
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objects, which has the goal to make space in gpu virtual address spaces.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
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:internal:
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Batchbuffer Parsing
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-------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
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:doc: batch buffer command parser
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.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
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:internal:
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Batchbuffer Pools
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-----------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
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:doc: batch pool
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
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:internal:
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User Batchbuffer Execution
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--------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_execbuffer.c
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:doc: User command execution
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Logical Rings, Logical Ring Contexts and Execlists
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--------------------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
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:doc: Logical Rings, Logical Ring Contexts and Execlists
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.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
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:internal:
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Global GTT views
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----------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
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:doc: Global GTT views
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
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:internal:
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GTT Fences and Swizzling
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------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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:internal:
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Global GTT Fence Handling
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~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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:doc: fence register handling
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Hardware Tiling and Swizzling Details
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
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:doc: tiling swizzling details
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Object Tiling IOCTLs
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--------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
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:doc: buffer object tiling
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WOPCM
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=====
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WOPCM Layout
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------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
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:doc: WOPCM Layout
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GuC
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===
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GuC-specific firmware loader
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----------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
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:internal:
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GuC-based command submission
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----------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
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:doc: GuC-based command submission
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
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:internal:
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GuC Firmware Layout
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-------------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
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:doc: GuC Firmware Layout
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GuC Address Space
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-----------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
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:doc: GuC Address Space
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Tracing
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=======
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This sections covers all things related to the tracepoints implemented
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in the i915 driver.
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i915_ppgtt_create and i915_ppgtt_release
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----------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
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:doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
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i915_context_create and i915_context_free
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-----------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
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:doc: i915_context_create and i915_context_free tracepoints
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switch_mm
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---------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
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:doc: switch_mm tracepoint
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Perf
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====
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Overview
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--------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
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:doc: i915 Perf Overview
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Comparison with Core Perf
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-------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
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:doc: i915 Perf History and Comparison with Core Perf
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i915 Driver Entry Points
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------------------------
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This section covers the entrypoints exported outside of i915_perf.c to
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integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
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:functions: i915_perf_init
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.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
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:functions: i915_perf_fini
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.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
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:functions: i915_perf_register
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_unregister
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_open_ioctl
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_release
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_add_config_ioctl
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_remove_config_ioctl
|
|
|
|
i915 Perf Stream
|
|
----------------
|
|
|
|
This section covers the stream-semantics-agnostic structures and functions
|
|
for representing an i915 perf stream FD and associated file operations.
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
|
|
:functions: i915_perf_stream
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
|
|
:functions: i915_perf_stream_ops
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: read_properties_unlocked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_open_ioctl_locked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_destroy_locked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_read
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_ioctl
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_enable_locked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_disable_locked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_poll
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_perf_poll_locked
|
|
|
|
i915 Perf Observation Architecture Stream
|
|
-----------------------------------------
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
|
|
:functions: i915_oa_ops
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_stream_init
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_read
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_stream_enable
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_stream_disable
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_wait_unlocked
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:functions: i915_oa_poll_wait
|
|
|
|
All i915 Perf Internals
|
|
-----------------------
|
|
|
|
This section simply includes all currently documented i915 perf internals, in
|
|
no particular order, but may include some more minor utilities or platform
|
|
specific details than found in the more high-level sections.
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
|
|
:internal:
|
|
|
|
Style
|
|
=====
|
|
|
|
The drm/i915 driver codebase has some style rules in addition to (and, in some
|
|
cases, deviating from) the kernel coding style.
|
|
|
|
Register macro definition style
|
|
-------------------------------
|
|
|
|
The style guide for ``i915_reg.h``.
|
|
|
|
.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
|
|
:doc: The i915 register macro definition style guide
|