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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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90405aa022
In callstack mode the LBR is not a ring buffer, but a stack that grows up and down. This means in this case we don't need to access all LBRs, only the ones up to TOS. Do this optimization for the normal LBR read, and the context switch save/restore code. For save/restore it can be done unconditionally, as it only runs when call stack mode is active. This recovers some of the cost of going to 32 LBRs on Skylake. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: eranian@google.com Cc: jolsa@redhat.com Link: http://lkml.kernel.org/r/1432786398-23861-6-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> |
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| mcheck | ||
| microcode | ||
| mtrr | ||
| .gitignore | ||
| amd.c | ||
| bugs_64.c | ||
| bugs.c | ||
| centaur.c | ||
| common.c | ||
| cpu.h | ||
| cyrix.c | ||
| hypervisor.c | ||
| intel_cacheinfo.c | ||
| intel_pt.h | ||
| intel.c | ||
| Makefile | ||
| match.c | ||
| mkcapflags.sh | ||
| mshyperv.c | ||
| perf_event_amd_ibs.c | ||
| perf_event_amd_iommu.c | ||
| perf_event_amd_iommu.h | ||
| perf_event_amd_uncore.c | ||
| perf_event_amd.c | ||
| perf_event_intel_bts.c | ||
| perf_event_intel_cqm.c | ||
| perf_event_intel_ds.c | ||
| perf_event_intel_lbr.c | ||
| perf_event_intel_pt.c | ||
| perf_event_intel_rapl.c | ||
| perf_event_intel_uncore_nhmex.c | ||
| perf_event_intel_uncore_snb.c | ||
| perf_event_intel_uncore_snbep.c | ||
| perf_event_intel_uncore.c | ||
| perf_event_intel_uncore.h | ||
| perf_event_intel.c | ||
| perf_event_knc.c | ||
| perf_event_p4.c | ||
| perf_event_p6.c | ||
| perf_event.c | ||
| perf_event.h | ||
| perfctr-watchdog.c | ||
| powerflags.c | ||
| proc.c | ||
| rdrand.c | ||
| scattered.c | ||
| topology.c | ||
| transmeta.c | ||
| umc.c | ||
| vmware.c | ||