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4fa96afd94
Although the GIC architecture requires us to map the MMIO regions only at page aligned addresses, we currently do not enforce this from the kernel side. Restrict any vGICv2 regions to be 4K aligned and any GICv3 regions to be 64K aligned. Document this requirement. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
117 lines
4.9 KiB
Plaintext
117 lines
4.9 KiB
Plaintext
ARM Virtual Generic Interrupt Controller (VGIC)
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===============================================
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Device types supported:
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KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
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KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
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Only one VGIC instance may be instantiated through either this API or the
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legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt
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controller, requiring emulated user-space devices to inject interrupts to the
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VGIC instead of directly to CPUs.
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Creating a guest GICv3 device requires a host GICv3 as well.
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GICv3 implementations with hardware compatibility support allow a guest GICv2
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as well.
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Groups:
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KVM_DEV_ARM_VGIC_GRP_ADDR
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Attributes:
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KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
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Base address in the guest physical address space of the GIC distributor
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register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
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This address needs to be 4K aligned and the region covers 4 KByte.
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KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
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Base address in the guest physical address space of the GIC virtual cpu
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interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
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This address needs to be 4K aligned and the region covers 4 KByte.
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KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
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Base address in the guest physical address space of the GICv3 distributor
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register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
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This address needs to be 64K aligned and the region covers 64 KByte.
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KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
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Base address in the guest physical address space of the GICv3
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redistributor register mappings. There are two 64K pages for each
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VCPU and all of the redistributor pages are contiguous.
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Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
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This address needs to be 64K aligned.
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values:
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | cpu id | offset |
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All distributor regs are (rw, 32-bit)
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The offset is relative to the "Distributor base address" as defined in the
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GICv2 specs. Getting or setting such a register has the same effect as
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reading or writing the register on the actual hardware from the cpu
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specified with cpu id field. Note that most distributor fields are not
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banked, but return the same value regardless of the cpu id used to access
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the register.
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Limitations:
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- Priorities are not implemented, and registers are RAZ/WI
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- Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.
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Errors:
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-ENODEV: Getting or setting this register is not yet supported
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-EBUSY: One or more VCPUs are running
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KVM_DEV_ARM_VGIC_GRP_CPU_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values:
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | cpu id | offset |
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All CPU interface regs are (rw, 32-bit)
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The offset specifies the offset from the "CPU interface base address" as
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defined in the GICv2 specs. Getting or setting such a register has the
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same effect as reading or writing the register on the actual hardware.
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The Active Priorities Registers APRn are implementation defined, so we set a
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fixed format for our implementation that fits with the model of a "GICv2
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implementation without the security extensions" which we present to the
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guest. This interface always exposes four register APR[0-3] describing the
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maximum possible 128 preemption levels. The semantics of the register
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indicate if any interrupts in a given preemption level are in the active
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state by setting the corresponding bit.
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Thus, preemption level X has one or more active interrupts if and only if:
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APRn[X mod 32] == 0b1, where n = X / 32
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Bits for undefined preemption levels are RAZ/WI.
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Limitations:
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- Priorities are not implemented, and registers are RAZ/WI
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- Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.
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Errors:
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-ENODEV: Getting or setting this register is not yet supported
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-EBUSY: One or more VCPUs are running
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KVM_DEV_ARM_VGIC_GRP_NR_IRQS
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Attributes:
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A value describing the number of interrupts (SGI, PPI and SPI) for
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this GIC instance, ranging from 64 to 1024, in increments of 32.
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Errors:
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-EINVAL: Value set is out of the expected range
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-EBUSY: Value has already be set, or GIC has already been initialized
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with default values.
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KVM_DEV_ARM_VGIC_GRP_CTRL
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Attributes:
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KVM_DEV_ARM_VGIC_CTRL_INIT
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request the initialization of the VGIC, no additional parameter in
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kvm_device_attr.addr.
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Errors:
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-ENXIO: VGIC not properly configured as required prior to calling
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this attribute
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-ENODEV: no online VCPU
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-ENOMEM: memory shortage when allocating vgic internal data
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