mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 02:15:23 +07:00
4e1a623031
Fix Cb/CR components order in two-planar YUV420, YUV422 and YUV444 modes. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
721 lines
18 KiB
C
721 lines
18 KiB
C
/*
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* Copyright (C) 2017 Samsung Electronics Co.Ltd
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* Author:
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* Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundationr
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*/
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#include <linux/kernel.h>
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#include <linux/component.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <drm/drmP.h>
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#include <drm/exynos_drm.h>
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#include "regs-scaler.h"
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#include "exynos_drm_fb.h"
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#include "exynos_drm_drv.h"
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#include "exynos_drm_iommu.h"
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#include "exynos_drm_ipp.h"
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#define scaler_read(offset) readl(scaler->regs + (offset))
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#define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset))
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#define SCALER_MAX_CLK 4
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#define SCALER_AUTOSUSPEND_DELAY 2000
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#define SCALER_RESET_WAIT_RETRIES 100
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struct scaler_data {
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const char *clk_name[SCALER_MAX_CLK];
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unsigned int num_clk;
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const struct exynos_drm_ipp_formats *formats;
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unsigned int num_formats;
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};
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struct scaler_context {
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struct exynos_drm_ipp ipp;
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struct drm_device *drm_dev;
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struct device *dev;
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void __iomem *regs;
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struct clk *clock[SCALER_MAX_CLK];
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struct exynos_drm_ipp_task *task;
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const struct scaler_data *scaler_data;
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};
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static u32 scaler_get_format(u32 drm_fmt)
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{
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switch (drm_fmt) {
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case DRM_FORMAT_NV12:
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return SCALER_YUV420_2P_UV;
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case DRM_FORMAT_NV21:
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return SCALER_YUV420_2P_VU;
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case DRM_FORMAT_YUV420:
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return SCALER_YUV420_3P;
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case DRM_FORMAT_YUYV:
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return SCALER_YUV422_1P_YUYV;
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case DRM_FORMAT_UYVY:
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return SCALER_YUV422_1P_UYVY;
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case DRM_FORMAT_YVYU:
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return SCALER_YUV422_1P_YVYU;
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case DRM_FORMAT_NV16:
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return SCALER_YUV422_2P_UV;
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case DRM_FORMAT_NV61:
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return SCALER_YUV422_2P_VU;
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case DRM_FORMAT_YUV422:
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return SCALER_YUV422_3P;
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case DRM_FORMAT_NV24:
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return SCALER_YUV444_2P_UV;
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case DRM_FORMAT_NV42:
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return SCALER_YUV444_2P_VU;
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case DRM_FORMAT_YUV444:
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return SCALER_YUV444_3P;
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case DRM_FORMAT_RGB565:
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return SCALER_RGB_565;
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case DRM_FORMAT_XRGB1555:
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return SCALER_ARGB1555;
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case DRM_FORMAT_ARGB1555:
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return SCALER_ARGB1555;
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case DRM_FORMAT_XRGB4444:
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return SCALER_ARGB4444;
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case DRM_FORMAT_ARGB4444:
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return SCALER_ARGB4444;
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case DRM_FORMAT_XRGB8888:
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return SCALER_ARGB8888;
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case DRM_FORMAT_ARGB8888:
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return SCALER_ARGB8888;
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case DRM_FORMAT_RGBX8888:
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return SCALER_RGBA8888;
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case DRM_FORMAT_RGBA8888:
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return SCALER_RGBA8888;
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default:
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break;
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}
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return 0;
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}
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static inline int scaler_reset(struct scaler_context *scaler)
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{
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int retry = SCALER_RESET_WAIT_RETRIES;
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scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG);
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do {
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cpu_relax();
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} while (retry > 1 &&
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scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET);
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do {
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cpu_relax();
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scaler_write(1, SCALER_INT_EN);
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} while (retry > 0 && scaler_read(SCALER_INT_EN) != 1);
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return retry ? 0 : -EIO;
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}
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static inline void scaler_enable_int(struct scaler_context *scaler)
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{
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u32 val;
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val = SCALER_INT_EN_TIMEOUT |
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SCALER_INT_EN_ILLEGAL_BLEND |
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SCALER_INT_EN_ILLEGAL_RATIO |
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SCALER_INT_EN_ILLEGAL_DST_HEIGHT |
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SCALER_INT_EN_ILLEGAL_DST_WIDTH |
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SCALER_INT_EN_ILLEGAL_DST_V_POS |
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SCALER_INT_EN_ILLEGAL_DST_H_POS |
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SCALER_INT_EN_ILLEGAL_DST_C_SPAN |
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SCALER_INT_EN_ILLEGAL_DST_Y_SPAN |
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SCALER_INT_EN_ILLEGAL_DST_CR_BASE |
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SCALER_INT_EN_ILLEGAL_DST_CB_BASE |
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SCALER_INT_EN_ILLEGAL_DST_Y_BASE |
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SCALER_INT_EN_ILLEGAL_DST_COLOR |
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SCALER_INT_EN_ILLEGAL_SRC_HEIGHT |
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SCALER_INT_EN_ILLEGAL_SRC_WIDTH |
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SCALER_INT_EN_ILLEGAL_SRC_CV_POS |
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SCALER_INT_EN_ILLEGAL_SRC_CH_POS |
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SCALER_INT_EN_ILLEGAL_SRC_YV_POS |
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SCALER_INT_EN_ILLEGAL_SRC_YH_POS |
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SCALER_INT_EN_ILLEGAL_DST_SPAN |
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SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN |
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SCALER_INT_EN_ILLEGAL_SRC_CR_BASE |
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SCALER_INT_EN_ILLEGAL_SRC_CB_BASE |
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SCALER_INT_EN_ILLEGAL_SRC_Y_BASE |
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SCALER_INT_EN_ILLEGAL_SRC_COLOR |
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SCALER_INT_EN_FRAME_END;
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scaler_write(val, SCALER_INT_EN);
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}
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static inline void scaler_set_src_fmt(struct scaler_context *scaler,
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u32 src_fmt)
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{
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u32 val;
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val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt);
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scaler_write(val, SCALER_SRC_CFG);
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}
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static inline void scaler_set_src_base(struct scaler_context *scaler,
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struct exynos_drm_ipp_buffer *src_buf)
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{
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static unsigned int bases[] = {
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SCALER_SRC_Y_BASE,
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SCALER_SRC_CB_BASE,
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SCALER_SRC_CR_BASE,
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};
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int i;
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for (i = 0; i < src_buf->format->num_planes; ++i)
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scaler_write(src_buf->dma_addr[i], bases[i]);
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}
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static inline void scaler_set_src_span(struct scaler_context *scaler,
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struct exynos_drm_ipp_buffer *src_buf)
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{
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u32 val;
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val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] /
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src_buf->format->cpp[0]);
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if (src_buf->format->num_planes > 1)
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val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]);
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scaler_write(val, SCALER_SRC_SPAN);
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}
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static inline void scaler_set_src_luma_pos(struct scaler_context *scaler,
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struct drm_exynos_ipp_task_rect *src_pos)
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{
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u32 val;
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val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
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val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
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scaler_write(val, SCALER_SRC_Y_POS);
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scaler_write(val, SCALER_SRC_C_POS); /* ATTENTION! */
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}
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static inline void scaler_set_src_wh(struct scaler_context *scaler,
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struct drm_exynos_ipp_task_rect *src_pos)
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{
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u32 val;
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val = SCALER_SRC_WH_SET_WIDTH(src_pos->w);
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val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h);
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scaler_write(val, SCALER_SRC_WH);
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}
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static inline void scaler_set_dst_fmt(struct scaler_context *scaler,
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u32 dst_fmt)
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{
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u32 val;
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val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt);
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scaler_write(val, SCALER_DST_CFG);
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}
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static inline void scaler_set_dst_base(struct scaler_context *scaler,
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struct exynos_drm_ipp_buffer *dst_buf)
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{
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static unsigned int bases[] = {
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SCALER_DST_Y_BASE,
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SCALER_DST_CB_BASE,
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SCALER_DST_CR_BASE,
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};
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int i;
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for (i = 0; i < dst_buf->format->num_planes; ++i)
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scaler_write(dst_buf->dma_addr[i], bases[i]);
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}
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static inline void scaler_set_dst_span(struct scaler_context *scaler,
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struct exynos_drm_ipp_buffer *dst_buf)
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{
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u32 val;
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val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] /
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dst_buf->format->cpp[0]);
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if (dst_buf->format->num_planes > 1)
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val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]);
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scaler_write(val, SCALER_DST_SPAN);
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}
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static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler,
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struct drm_exynos_ipp_task_rect *dst_pos)
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{
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u32 val;
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val = SCALER_DST_WH_SET_WIDTH(dst_pos->w);
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val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h);
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scaler_write(val, SCALER_DST_WH);
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}
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static inline void scaler_set_dst_wh(struct scaler_context *scaler,
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struct drm_exynos_ipp_task_rect *dst_pos)
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{
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u32 val;
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val = SCALER_DST_POS_SET_H_POS(dst_pos->x);
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val |= SCALER_DST_POS_SET_V_POS(dst_pos->y);
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scaler_write(val, SCALER_DST_POS);
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}
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static inline void scaler_set_hv_ratio(struct scaler_context *scaler,
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unsigned int rotation,
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struct drm_exynos_ipp_task_rect *src_pos,
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struct drm_exynos_ipp_task_rect *dst_pos)
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{
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u32 val, h_ratio, v_ratio;
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if (drm_rotation_90_or_270(rotation)) {
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h_ratio = (src_pos->h << 16) / dst_pos->w;
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v_ratio = (src_pos->w << 16) / dst_pos->h;
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} else {
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h_ratio = (src_pos->w << 16) / dst_pos->w;
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v_ratio = (src_pos->h << 16) / dst_pos->h;
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}
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val = SCALER_H_RATIO_SET(h_ratio);
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scaler_write(val, SCALER_H_RATIO);
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val = SCALER_V_RATIO_SET(v_ratio);
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scaler_write(val, SCALER_V_RATIO);
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}
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static inline void scaler_set_rotation(struct scaler_context *scaler,
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unsigned int rotation)
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{
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u32 val = 0;
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if (rotation & DRM_MODE_ROTATE_90)
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val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90);
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else if (rotation & DRM_MODE_ROTATE_180)
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val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180);
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else if (rotation & DRM_MODE_ROTATE_270)
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val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270);
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if (rotation & DRM_MODE_REFLECT_X)
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val |= SCALER_ROT_CFG_FLIP_X_EN;
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if (rotation & DRM_MODE_REFLECT_Y)
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val |= SCALER_ROT_CFG_FLIP_Y_EN;
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scaler_write(val, SCALER_ROT_CFG);
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}
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static inline void scaler_set_csc(struct scaler_context *scaler,
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const struct drm_format_info *fmt)
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{
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static const u32 csc_mtx[2][3][3] = {
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{ /* YCbCr to RGB */
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{0x254, 0x000, 0x331},
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{0x254, 0xf38, 0xe60},
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{0x254, 0x409, 0x000},
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},
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{ /* RGB to YCbCr */
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{0x084, 0x102, 0x032},
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{0xfb4, 0xf6b, 0x0e1},
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{0x0e1, 0xf44, 0xfdc},
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},
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};
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int i, j, dir;
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switch (fmt->format) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_XRGB1555:
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_XRGB4444:
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_RGBA8888:
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dir = 1;
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break;
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default:
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dir = 0;
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}
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for (i = 0; i < 3; i++)
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for (j = 0; j < 3; j++)
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scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i));
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}
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static inline void scaler_set_timer(struct scaler_context *scaler,
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unsigned int timer, unsigned int divider)
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{
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u32 val;
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val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE;
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val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer);
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val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
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scaler_write(val, SCALER_TIMEOUT_CTRL);
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}
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static inline void scaler_start_hw(struct scaler_context *scaler)
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{
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scaler_write(SCALER_CFG_START_CMD, SCALER_CFG);
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}
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static int scaler_commit(struct exynos_drm_ipp *ipp,
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struct exynos_drm_ipp_task *task)
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{
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struct scaler_context *scaler =
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container_of(ipp, struct scaler_context, ipp);
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u32 src_fmt = scaler_get_format(task->src.buf.fourcc);
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struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
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u32 dst_fmt = scaler_get_format(task->dst.buf.fourcc);
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struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
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pm_runtime_get_sync(scaler->dev);
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if (scaler_reset(scaler)) {
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pm_runtime_put(scaler->dev);
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return -EIO;
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}
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scaler->task = task;
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scaler_set_src_fmt(scaler, src_fmt);
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scaler_set_src_base(scaler, &task->src);
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scaler_set_src_span(scaler, &task->src);
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scaler_set_src_luma_pos(scaler, src_pos);
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scaler_set_src_wh(scaler, src_pos);
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scaler_set_dst_fmt(scaler, dst_fmt);
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scaler_set_dst_base(scaler, &task->dst);
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scaler_set_dst_span(scaler, &task->dst);
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scaler_set_dst_luma_pos(scaler, dst_pos);
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scaler_set_dst_wh(scaler, dst_pos);
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scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos);
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scaler_set_rotation(scaler, task->transform.rotation);
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scaler_set_csc(scaler, task->src.format);
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scaler_set_timer(scaler, 0xffff, 0xf);
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scaler_enable_int(scaler);
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scaler_start_hw(scaler);
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return 0;
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}
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static struct exynos_drm_ipp_funcs ipp_funcs = {
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.commit = scaler_commit,
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};
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static inline void scaler_disable_int(struct scaler_context *scaler)
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{
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scaler_write(0, SCALER_INT_EN);
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}
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static inline u32 scaler_get_int_status(struct scaler_context *scaler)
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{
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u32 val = scaler_read(SCALER_INT_STATUS);
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scaler_write(val, SCALER_INT_STATUS);
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return val;
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}
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static inline int scaler_task_done(u32 val)
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{
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return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL;
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}
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static irqreturn_t scaler_irq_handler(int irq, void *arg)
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{
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struct scaler_context *scaler = arg;
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u32 val = scaler_get_int_status(scaler);
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scaler_disable_int(scaler);
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if (scaler->task) {
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struct exynos_drm_ipp_task *task = scaler->task;
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scaler->task = NULL;
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pm_runtime_mark_last_busy(scaler->dev);
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pm_runtime_put_autosuspend(scaler->dev);
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exynos_drm_ipp_task_done(task, scaler_task_done(val));
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}
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return IRQ_HANDLED;
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}
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static int scaler_bind(struct device *dev, struct device *master, void *data)
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{
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struct scaler_context *scaler = dev_get_drvdata(dev);
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struct drm_device *drm_dev = data;
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struct exynos_drm_ipp *ipp = &scaler->ipp;
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scaler->drm_dev = drm_dev;
|
|
drm_iommu_attach_device(drm_dev, dev);
|
|
|
|
exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
|
|
DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
|
|
DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
|
|
scaler->scaler_data->formats,
|
|
scaler->scaler_data->num_formats, "scaler");
|
|
|
|
dev_info(dev, "The exynos scaler has been probed successfully\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void scaler_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct scaler_context *scaler = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
struct exynos_drm_ipp *ipp = &scaler->ipp;
|
|
|
|
exynos_drm_ipp_unregister(drm_dev, ipp);
|
|
drm_iommu_detach_device(scaler->drm_dev, scaler->dev);
|
|
}
|
|
|
|
static const struct component_ops scaler_component_ops = {
|
|
.bind = scaler_bind,
|
|
.unbind = scaler_unbind,
|
|
};
|
|
|
|
static int scaler_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *regs_res;
|
|
struct scaler_context *scaler;
|
|
int irq;
|
|
int ret, i;
|
|
|
|
scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL);
|
|
if (!scaler)
|
|
return -ENOMEM;
|
|
|
|
scaler->scaler_data =
|
|
(struct scaler_data *)of_device_get_match_data(dev);
|
|
|
|
scaler->dev = dev;
|
|
regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
scaler->regs = devm_ioremap_resource(dev, regs_res);
|
|
if (IS_ERR(scaler->regs))
|
|
return PTR_ERR(scaler->regs);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get irq\n");
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler,
|
|
IRQF_ONESHOT, "drm_scaler", scaler);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < scaler->scaler_data->num_clk; ++i) {
|
|
scaler->clock[i] = devm_clk_get(dev,
|
|
scaler->scaler_data->clk_name[i]);
|
|
if (IS_ERR(scaler->clock[i])) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return PTR_ERR(scaler->clock[i]);
|
|
}
|
|
}
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY);
|
|
pm_runtime_enable(dev);
|
|
platform_set_drvdata(pdev, scaler);
|
|
|
|
ret = component_add(dev, &scaler_component_ops);
|
|
if (ret)
|
|
goto err_ippdrv_register;
|
|
|
|
return 0;
|
|
|
|
err_ippdrv_register:
|
|
pm_runtime_dont_use_autosuspend(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int scaler_remove(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
|
|
component_del(dev, &scaler_component_ops);
|
|
pm_runtime_dont_use_autosuspend(dev);
|
|
pm_runtime_disable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int clk_disable_unprepare_wrapper(struct clk *clk)
|
|
{
|
|
clk_disable_unprepare(clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable)
|
|
{
|
|
int (*clk_fun)(struct clk *clk), i;
|
|
|
|
clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper;
|
|
|
|
for (i = 0; i < scaler->scaler_data->num_clk; ++i)
|
|
clk_fun(scaler->clock[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int scaler_runtime_suspend(struct device *dev)
|
|
{
|
|
struct scaler_context *scaler = dev_get_drvdata(dev);
|
|
|
|
return scaler_clk_ctrl(scaler, false);
|
|
}
|
|
|
|
static int scaler_runtime_resume(struct device *dev)
|
|
{
|
|
struct scaler_context *scaler = dev_get_drvdata(dev);
|
|
|
|
return scaler_clk_ctrl(scaler, true);
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops scaler_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = {
|
|
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
|
|
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
|
|
{ IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
|
|
.v = { 65536 * 1 / 4, 65536 * 16 }) },
|
|
};
|
|
|
|
static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = {
|
|
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
|
|
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
|
|
{ IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
|
|
.v = { 65536 * 1 / 4, 65536 * 16 }) },
|
|
};
|
|
|
|
static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = {
|
|
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
|
|
{ IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
|
|
.v = { 65536 * 1 / 4, 65536 * 16 }) },
|
|
};
|
|
|
|
static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
|
|
/* SCALER_YUV420_2P_UV */
|
|
{ IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
|
|
|
|
/* SCALER_YUV420_2P_VU */
|
|
{ IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) },
|
|
|
|
/* SCALER_YUV420_3P */
|
|
{ IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) },
|
|
|
|
/* SCALER_YUV422_1P_YUYV */
|
|
{ IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV422_1P_UYVY */
|
|
{ IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV422_1P_YVYU */
|
|
{ IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV422_2P_UV */
|
|
{ IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV422_2P_VU */
|
|
{ IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV422_3P */
|
|
{ IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) },
|
|
|
|
/* SCALER_YUV444_2P_UV */
|
|
{ IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_YUV444_2P_VU */
|
|
{ IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_YUV444_3P */
|
|
{ IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_RGB_565 */
|
|
{ IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB1555 */
|
|
{ IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB1555 */
|
|
{ IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB4444 */
|
|
{ IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB4444 */
|
|
{ IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB8888 */
|
|
{ IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_ARGB8888 */
|
|
{ IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_RGBA8888 */
|
|
{ IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) },
|
|
|
|
/* SCALER_RGBA8888 */
|
|
{ IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
|
|
};
|
|
|
|
static const struct scaler_data exynos5420_data = {
|
|
.clk_name = {"mscl"},
|
|
.num_clk = 1,
|
|
.formats = exynos5420_formats,
|
|
.num_formats = ARRAY_SIZE(exynos5420_formats),
|
|
};
|
|
|
|
static const struct scaler_data exynos5433_data = {
|
|
.clk_name = {"pclk", "aclk", "aclk_xiu"},
|
|
.num_clk = 3,
|
|
.formats = exynos5420_formats, /* intentional */
|
|
.num_formats = ARRAY_SIZE(exynos5420_formats),
|
|
};
|
|
|
|
static const struct of_device_id exynos_scaler_match[] = {
|
|
{
|
|
.compatible = "samsung,exynos5420-scaler",
|
|
.data = &exynos5420_data,
|
|
}, {
|
|
.compatible = "samsung,exynos5433-scaler",
|
|
.data = &exynos5433_data,
|
|
}, {
|
|
},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos_scaler_match);
|
|
|
|
struct platform_driver scaler_driver = {
|
|
.probe = scaler_probe,
|
|
.remove = scaler_remove,
|
|
.driver = {
|
|
.name = "exynos-scaler",
|
|
.owner = THIS_MODULE,
|
|
.pm = &scaler_pm_ops,
|
|
.of_match_table = exynos_scaler_match,
|
|
},
|
|
};
|