mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e9a6269d5b
RX is handled in a workqueue therefore allocating for GFP_ATOMIC is overkill and not required. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Acked-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
225 lines
7.4 KiB
C
225 lines
7.4 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include "wl1271.h"
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#include "wl1271_acx.h"
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#include "wl1271_reg.h"
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#include "wl1271_rx.h"
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#include "wl1271_spi.h"
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static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status,
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u32 drv_rx_counter)
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{
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return le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
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RX_MEM_BLOCK_MASK;
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}
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static u32 wl1271_rx_get_buf_size(struct wl1271_fw_status *status,
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u32 drv_rx_counter)
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{
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return (le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
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RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV;
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}
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/* The values of this table must match the wl1271_rates[] array */
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static u8 wl1271_rx_rate_to_idx[] = {
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/* MCS rates are used only with 11n */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS7 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS6 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS5 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS4 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS3 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS2 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS1 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS0 */
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11, /* WL1271_RATE_54 */
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10, /* WL1271_RATE_48 */
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9, /* WL1271_RATE_36 */
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8, /* WL1271_RATE_24 */
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/* TI-specific rate */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_22 */
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7, /* WL1271_RATE_18 */
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6, /* WL1271_RATE_12 */
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3, /* WL1271_RATE_11 */
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5, /* WL1271_RATE_9 */
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4, /* WL1271_RATE_6 */
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2, /* WL1271_RATE_5_5 */
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1, /* WL1271_RATE_2 */
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0 /* WL1271_RATE_1 */
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};
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/* The values of this table must match the wl1271_rates[] array */
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static u8 wl1271_5_ghz_rx_rate_to_idx[] = {
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/* MCS rates are used only with 11n */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS7 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS6 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS5 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS4 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS3 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS2 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS1 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS0 */
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7, /* WL1271_RATE_54 */
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6, /* WL1271_RATE_48 */
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5, /* WL1271_RATE_36 */
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4, /* WL1271_RATE_24 */
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/* TI-specific rate */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_22 */
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3, /* WL1271_RATE_18 */
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2, /* WL1271_RATE_12 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_11 */
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1, /* WL1271_RATE_9 */
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0, /* WL1271_RATE_6 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_5_5 */
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WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_2 */
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WL1271_RX_RATE_UNSUPPORTED /* WL1271_RATE_1 */
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};
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static void wl1271_rx_status(struct wl1271 *wl,
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struct wl1271_rx_descriptor *desc,
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struct ieee80211_rx_status *status,
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u8 beacon)
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{
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memset(status, 0, sizeof(struct ieee80211_rx_status));
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if ((desc->flags & WL1271_RX_DESC_BAND_MASK) ==
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WL1271_RX_DESC_BAND_BG) {
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status->band = IEEE80211_BAND_2GHZ;
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status->rate_idx = wl1271_rx_rate_to_idx[desc->rate];
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} else if ((desc->flags & WL1271_RX_DESC_BAND_MASK) ==
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WL1271_RX_DESC_BAND_A) {
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status->band = IEEE80211_BAND_5GHZ;
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status->rate_idx = wl1271_5_ghz_rx_rate_to_idx[desc->rate];
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} else
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wl1271_warning("unsupported band 0x%x",
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desc->flags & WL1271_RX_DESC_BAND_MASK);
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if (unlikely(status->rate_idx == WL1271_RX_RATE_UNSUPPORTED))
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wl1271_warning("unsupported rate");
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/*
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* FIXME: Add mactime handling. For IBSS (ad-hoc) we need to get the
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* timestamp from the beacon (acx_tsf_info). In BSS mode (infra) we
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* only need the mactime for monitor mode. For now the mactime is
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* not valid, so RX_FLAG_TSFT should not be set
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*/
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status->signal = desc->rssi;
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/*
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* FIXME: In wl1251, the SNR should be divided by two. In wl1271 we
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* need to divide by two for now, but TI has been discussing about
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* changing it. This needs to be rechecked.
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*/
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status->noise = desc->rssi - (desc->snr >> 1);
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status->freq = ieee80211_channel_to_frequency(desc->channel);
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if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) {
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status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED;
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if (likely(!(desc->status & WL1271_RX_DESC_DECRYPT_FAIL)))
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status->flag |= RX_FLAG_DECRYPTED;
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if (unlikely(desc->status & WL1271_RX_DESC_MIC_FAIL))
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status->flag |= RX_FLAG_MMIC_ERROR;
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}
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}
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static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length)
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{
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struct ieee80211_rx_status rx_status;
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struct wl1271_rx_descriptor *desc;
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struct sk_buff *skb;
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u16 *fc;
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u8 *buf;
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u8 beacon = 0;
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skb = __dev_alloc_skb(length, GFP_KERNEL);
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if (!skb) {
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wl1271_error("Couldn't allocate RX frame");
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return;
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}
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buf = skb_put(skb, length);
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wl1271_spi_read(wl, WL1271_SLV_MEM_DATA, buf, length, true);
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/* the data read starts with the descriptor */
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desc = (struct wl1271_rx_descriptor *) buf;
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/* now we pull the descriptor out of the buffer */
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skb_pull(skb, sizeof(*desc));
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fc = (u16 *)skb->data;
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if ((*fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_BEACON)
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beacon = 1;
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wl1271_rx_status(wl, desc, &rx_status, beacon);
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wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s", skb, skb->len,
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beacon ? "beacon" : "");
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memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
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ieee80211_rx_ni(wl->hw, skb);
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}
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void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status)
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{
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struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
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u32 buf_size;
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u32 fw_rx_counter = status->fw_rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
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u32 drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
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u32 mem_block;
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while (drv_rx_counter != fw_rx_counter) {
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mem_block = wl1271_rx_get_mem_block(status, drv_rx_counter);
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buf_size = wl1271_rx_get_buf_size(status, drv_rx_counter);
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if (buf_size == 0) {
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wl1271_warning("received empty data");
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break;
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}
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wl->rx_mem_pool_addr.addr = (mem_block << 8) +
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le32_to_cpu(wl_mem_map->packet_memory_pool_start);
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wl->rx_mem_pool_addr.addr_extra =
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wl->rx_mem_pool_addr.addr + 4;
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/* Choose the block we want to read */
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wl1271_spi_write(wl, WL1271_SLV_REG_DATA,
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&wl->rx_mem_pool_addr,
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sizeof(wl->rx_mem_pool_addr), false);
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wl1271_rx_handle_data(wl, buf_size);
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wl->rx_counter++;
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drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
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}
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wl1271_spi_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);
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}
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