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ffe10e679c
SJA1105 switches R and S have one SerDes port with an 802.3z quasi-compatible PCS, hardwired on port 4. The other ports are still MII/RMII/RGMII. The PCS performs rate adaptation to lower link speeds; the MAC on this port is hardwired at gigabit. Only full duplex is supported. The SGMII port can be configured as part of the static config tables, as well as through a dedicated SPI address region for its pseudo-clause-22 registers. However it looks like the static configuration is not able to change some out-of-reset values (like the value of MII_BMCR), so at the end of the day, having code for it is utterly pointless. We are just going to use the pseudo-C22 interface. Because the PCS gets reset when the switch resets, we have to add even more restoration logic to sja1105_static_config_reload, otherwise the SGMII port breaks after operations such as enabling PTP timestamping which require a switch reset. >From PHYLINK perspective, the switch supports *only* SGMII (it doesn't support 1000Base-X). It also doesn't expose access to the raw config word for in-band AN in registers MII_ADV/MII_LPA. It is able to work in the following modes: - Forced speed - SGMII in-band AN slave (speed received from PHY) - SGMII in-band AN master (acting as a PHY) The latter mode is not supported by this patch. It is even unclear to me how that would be described. There is some code for it left in the patch, but 'an_master' is always passed as false. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright 2020, NXP Semiconductors
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*/
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#ifndef _SJA1105_SGMII_H
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#define _SJA1105_SGMII_H
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#define SJA1105_SGMII_PORT 4
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/* DIGITAL_CONTROL_1 (address 1f8000h) */
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#define SJA1105_DC1 0x8000
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#define SJA1105_DC1_VS_RESET BIT(15)
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#define SJA1105_DC1_REMOTE_LOOPBACK BIT(14)
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#define SJA1105_DC1_EN_VSMMD1 BIT(13)
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#define SJA1105_DC1_POWER_SAVE BIT(11)
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#define SJA1105_DC1_CLOCK_STOP_EN BIT(10)
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#define SJA1105_DC1_MAC_AUTO_SW BIT(9)
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#define SJA1105_DC1_INIT BIT(8)
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#define SJA1105_DC1_TX_DISABLE BIT(4)
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#define SJA1105_DC1_AUTONEG_TIMER_OVRR BIT(3)
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#define SJA1105_DC1_BYP_POWERUP BIT(1)
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#define SJA1105_DC1_PHY_MODE_CONTROL BIT(0)
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/* DIGITAL_CONTROL_2 register (address 1f80E1h) */
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#define SJA1105_DC2 0x80e1
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#define SJA1105_DC2_TX_POL_INV_DISABLE BIT(4)
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#define SJA1105_DC2_RX_POL_INV BIT(0)
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/* DIGITAL_ERROR_CNT register (address 1f80E2h) */
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#define SJA1105_DEC 0x80e2
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#define SJA1105_DEC_ICG_EC_ENA BIT(4)
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#define SJA1105_DEC_CLEAR_ON_READ BIT(0)
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/* AUTONEG_CONTROL register (address 1f8001h) */
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#define SJA1105_AC 0x8001
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#define SJA1105_AC_MII_CONTROL BIT(8)
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#define SJA1105_AC_SGMII_LINK BIT(4)
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#define SJA1105_AC_PHY_MODE BIT(3)
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#define SJA1105_AC_AUTONEG_MODE(x) (((x) << 1) & GENMASK(2, 1))
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#define SJA1105_AC_AUTONEG_MODE_SGMII SJA1105_AC_AUTONEG_MODE(2)
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/* AUTONEG_INTR_STATUS register (address 1f8002h) */
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#define SJA1105_AIS 0x8002
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#define SJA1105_AIS_LINK_STATUS(x) (!!((x) & BIT(4)))
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#define SJA1105_AIS_SPEED(x) (((x) & GENMASK(3, 2)) >> 2)
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#define SJA1105_AIS_DUPLEX_MODE(x) (!!((x) & BIT(1)))
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#define SJA1105_AIS_COMPLETE(x) (!!((x) & BIT(0)))
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/* DEBUG_CONTROL register (address 1f8005h) */
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#define SJA1105_DC 0x8005
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#define SJA1105_DC_SUPPRESS_LOS BIT(4)
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#define SJA1105_DC_RESTART_SYNC BIT(0)
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#endif
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