mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 04:06:43 +07:00
bfa1ce5f38
This commit introduces a variant of the mv_mbus_dram_info() function
called mv_mbus_dram_info_nooverlap(). Both functions are used by
Marvell drivers supporting devices doing DMA, and provide them a
description the DRAM ranges that they need to configure their DRAM
windows.
The ranges provided by the mv_mbus_dram_info() function may overlap
with the I/O windows if there is a lot (>= 4 GB) of RAM
installed. This is not a problem for most of the DMA masters, except
for the upcoming new CESA crypto driver because it does DMA to the
SRAM, which is mapped through an I/O window. For this unit, we need to
have DRAM ranges that do not overlap with the I/O windows.
A first implementation done in commit 1737cac693 ("bus: mvebu-mbus:
make sure SDRAM CS for DMA don't overlap the MBus bridge window"),
changed the information returned by mv_mbus_dram_info() to match this
requirement. However, it broke the requirement of the other DMA
masters than the DRAM ranges should have power of two sizes.
To solve this situation, this commit introduces a new
mv_mbus_dram_info_nooverlap() function, which returns the same
information as mv_mbus_dram_info(), but guaranteed to not overlap with
the I/O windows.
In the end, it gives us two variants of the mv_mbus_dram_info*()
functions:
- The normal one, mv_mbus_dram_info(), which has been around for many
years. This function returns the raw DRAM ranges, which are
guaranteed to use power of two sizes, but will overlap with I/O
windows. This function will therefore be used by all DMA masters
(SATA, XOR, Ethernet, etc.) except the CESA crypto driver.
- The new 'nooverlap' variant, mv_mbus_dram_info_nooverlap(). This
function returns DRAM ranges after they have been "tweaked" to make
sure they don't overlap with I/O windows. By doing this tweaking,
we remove the power of two size guarantee. This variant will be
used by the new CESA crypto driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
|
|
* Marvell MBUS common definitions.
|
|
*
|
|
* Copyright (C) 2008 Marvell Semiconductor
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __LINUX_MBUS_H
|
|
#define __LINUX_MBUS_H
|
|
|
|
struct resource;
|
|
|
|
struct mbus_dram_target_info
|
|
{
|
|
/*
|
|
* The 4-bit MBUS target ID of the DRAM controller.
|
|
*/
|
|
u8 mbus_dram_target_id;
|
|
|
|
/*
|
|
* The base address, size, and MBUS attribute ID for each
|
|
* of the possible DRAM chip selects. Peripherals are
|
|
* required to support at least 4 decode windows.
|
|
*/
|
|
int num_cs;
|
|
struct mbus_dram_window {
|
|
u8 cs_index;
|
|
u8 mbus_attr;
|
|
u32 base;
|
|
u32 size;
|
|
} cs[4];
|
|
};
|
|
|
|
/* Flags for PCI/PCIe address decoding regions */
|
|
#define MVEBU_MBUS_PCI_IO 0x1
|
|
#define MVEBU_MBUS_PCI_MEM 0x2
|
|
#define MVEBU_MBUS_PCI_WA 0x3
|
|
|
|
/*
|
|
* Magic value that explicits that we don't need a remapping-capable
|
|
* address decoding window.
|
|
*/
|
|
#define MVEBU_MBUS_NO_REMAP (0xffffffff)
|
|
|
|
/* Maximum size of a mbus window name */
|
|
#define MVEBU_MBUS_MAX_WINNAME_SZ 32
|
|
|
|
/*
|
|
* The Marvell mbus is to be found only on SOCs from the Orion family
|
|
* at the moment. Provide a dummy stub for other architectures.
|
|
*/
|
|
#ifdef CONFIG_PLAT_ORION
|
|
extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
|
|
extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
|
|
#else
|
|
static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
int mvebu_mbus_save_cpu_target(u32 *store_addr);
|
|
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
|
|
void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
|
|
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
|
|
unsigned int attribute,
|
|
phys_addr_t base, size_t size,
|
|
phys_addr_t remap);
|
|
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
|
|
phys_addr_t base, size_t size);
|
|
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
|
|
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
|
|
size_t mbus_size, phys_addr_t sdram_phys_base,
|
|
size_t sdram_size);
|
|
int mvebu_mbus_dt_init(bool is_coherent);
|
|
|
|
#endif /* __LINUX_MBUS_H */
|