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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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aecf6fd878
The firmware name is hard coded which doesnt allow to load different platforms for various platforms so get this name from available machine table and pass it to dsp context for loading Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
147 lines
4.6 KiB
C
147 lines
4.6 KiB
C
/*
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* Skylake SST DSP Support
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*
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* Copyright (C) 2014-15, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __SKL_SST_DSP_H__
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#define __SKL_SST_DSP_H__
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#include <linux/interrupt.h>
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#include <sound/memalloc.h>
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#include "skl-sst-cldma.h"
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struct sst_dsp;
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struct skl_sst;
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struct sst_dsp_device;
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/* Intel HD Audio General DSP Registers */
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#define SKL_ADSP_GEN_BASE 0x0
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#define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04)
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#define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08)
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#define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C)
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#define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10)
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#define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14)
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/* Intel HD Audio Inter-Processor Communication Registers */
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#define SKL_ADSP_IPC_BASE 0x40
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#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
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#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
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#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
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#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
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#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
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/* HIPCI */
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#define SKL_ADSP_REG_HIPCI_BUSY BIT(31)
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/* HIPCIE */
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#define SKL_ADSP_REG_HIPCIE_DONE BIT(30)
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/* HIPCCTL */
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#define SKL_ADSP_REG_HIPCCTL_DONE BIT(1)
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#define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0)
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/* HIPCT */
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#define SKL_ADSP_REG_HIPCT_BUSY BIT(31)
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/* Intel HD Audio SRAM Window 1 */
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#define SKL_ADSP_SRAM1_BASE 0xA000
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#define SKL_ADSP_MMIO_LEN 0x10000
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#define SKL_ADSP_W0_STAT_SZ 0x800
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#define SKL_ADSP_W0_UP_SZ 0x800
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#define SKL_ADSP_W1_SZ 0x1000
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#define SKL_FW_STS_MASK 0xf
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#define SKL_FW_INIT 0x1
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#define SKL_FW_RFW_START 0xf
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#define SKL_ADSPIC_IPC 1
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#define SKL_ADSPIS_IPC 1
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/* ADSPCS - Audio DSP Control & Status */
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#define SKL_DSP_CORES 1
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#define SKL_DSP_CORE0_MASK 1
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#define SKL_DSP_CORES_MASK ((1 << SKL_DSP_CORES) - 1)
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/* Core Reset - asserted high */
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#define SKL_ADSPCS_CRST_SHIFT 0
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#define SKL_ADSPCS_CRST_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT)
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#define SKL_ADSPCS_CRST(x) ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK)
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/* Core run/stall - when set to '1' core is stalled */
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#define SKL_ADSPCS_CSTALL_SHIFT 8
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#define SKL_ADSPCS_CSTALL_MASK (SKL_DSP_CORES_MASK << \
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SKL_ADSPCS_CSTALL_SHIFT)
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#define SKL_ADSPCS_CSTALL(x) ((x << SKL_ADSPCS_CSTALL_SHIFT) & \
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SKL_ADSPCS_CSTALL_MASK)
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/* Set Power Active - when set to '1' turn cores on */
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#define SKL_ADSPCS_SPA_SHIFT 16
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#define SKL_ADSPCS_SPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT)
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#define SKL_ADSPCS_SPA(x) ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK)
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/* Current Power Active - power status of cores, set by hardware */
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#define SKL_ADSPCS_CPA_SHIFT 24
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#define SKL_ADSPCS_CPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT)
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#define SKL_ADSPCS_CPA(x) ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK)
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#define SST_DSP_POWER_D0 0x0 /* full On */
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#define SST_DSP_POWER_D3 0x3 /* Off */
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enum skl_dsp_states {
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SKL_DSP_RUNNING = 1,
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SKL_DSP_RESET,
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};
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struct skl_dsp_fw_ops {
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int (*load_fw)(struct sst_dsp *ctx);
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/* FW module parser/loader */
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int (*parse_fw)(struct sst_dsp *ctx);
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int (*set_state_D0)(struct sst_dsp *ctx);
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int (*set_state_D3)(struct sst_dsp *ctx);
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unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
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};
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struct skl_dsp_loader_ops {
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int (*alloc_dma_buf)(struct device *dev,
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struct snd_dma_buffer *dmab, size_t size);
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int (*free_dma_buf)(struct device *dev,
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struct snd_dma_buffer *dmab);
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};
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void skl_cldma_process_intr(struct sst_dsp *ctx);
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void skl_cldma_int_disable(struct sst_dsp *ctx);
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int skl_cldma_prepare(struct sst_dsp *ctx);
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void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
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struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
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struct sst_dsp_device *sst_dev, int irq);
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int skl_dsp_disable_core(struct sst_dsp *ctx);
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bool is_skl_dsp_running(struct sst_dsp *ctx);
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irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
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int skl_dsp_wake(struct sst_dsp *ctx);
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int skl_dsp_sleep(struct sst_dsp *ctx);
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void skl_dsp_free(struct sst_dsp *dsp);
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int skl_dsp_boot(struct sst_dsp *ctx);
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int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
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struct skl_sst **dsp);
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void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
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#endif /*__SKL_SST_DSP_H__*/
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