mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 00:40:56 +07:00
8ff1f4c4c4
Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/*
|
|
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef __QCOM_CLK_ALPHA_PLL_H__
|
|
#define __QCOM_CLK_ALPHA_PLL_H__
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include "clk-regmap.h"
|
|
|
|
struct pll_vco {
|
|
unsigned long min_freq;
|
|
unsigned long max_freq;
|
|
u32 val;
|
|
};
|
|
|
|
/**
|
|
* struct clk_alpha_pll - phase locked loop (PLL)
|
|
* @offset: base address of registers
|
|
* @vco_table: array of VCO settings
|
|
* @clkr: regmap clock handle
|
|
*/
|
|
struct clk_alpha_pll {
|
|
u32 offset;
|
|
|
|
const struct pll_vco *vco_table;
|
|
size_t num_vco;
|
|
|
|
struct clk_regmap clkr;
|
|
};
|
|
|
|
/**
|
|
* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
|
|
* @offset: base address of registers
|
|
* @width: width of post-divider
|
|
* @clkr: regmap clock handle
|
|
*/
|
|
struct clk_alpha_pll_postdiv {
|
|
u32 offset;
|
|
u8 width;
|
|
|
|
struct clk_regmap clkr;
|
|
};
|
|
|
|
extern const struct clk_ops clk_alpha_pll_ops;
|
|
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
|
|
|
|
#endif
|