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8efaf5ed4d
On i.MX6UL, AXI clock rate's design target is 264MHz, but by default it is only set to 198MHz which is NOT good enough for performance, this patch increases AXI clock rate from 198MHz to 264MHz to meet the design target, this is done by switching its parent clock "periph" from 396MHz PFD to 528MHz PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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.. | ||
clk-busy.c | ||
clk-cpu.c | ||
clk-fixup-div.c | ||
clk-fixup-mux.c | ||
clk-gate2.c | ||
clk-gate-exclusive.c | ||
clk-imx1.c | ||
clk-imx6q.c | ||
clk-imx6sl.c | ||
clk-imx6sx.c | ||
clk-imx6ul.c | ||
clk-imx7d.c | ||
clk-imx21.c | ||
clk-imx25.c | ||
clk-imx27.c | ||
clk-imx31.c | ||
clk-imx35.c | ||
clk-imx51-imx53.c | ||
clk-pfd.c | ||
clk-pllv1.c | ||
clk-pllv2.c | ||
clk-pllv3.c | ||
clk-vf610.c | ||
clk.c | ||
clk.h | ||
Makefile |