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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f29ad10de6
- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
30 lines
834 B
C
30 lines
834 B
C
/*
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* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 PWM Register Definitions.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON1_REGS_PWM_H
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#define __ASM_MACH_LOONGSON1_REGS_PWM_H
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/* Loongson 1 PWM Timer Register Definitions */
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#define PWM_CNT 0x0
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#define PWM_HRC 0x4
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#define PWM_LRC 0x8
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#define PWM_CTRL 0xc
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/* PWM Control Register Bits */
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#define CNT_RST (0x1 << 7)
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#define INT_SR (0x1 << 6)
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#define INT_EN (0x1 << 5)
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#define PWM_SINGLE (0x1 << 4)
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#define PWM_OE (0x1 << 3)
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#define CNT_EN 0x1
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#endif /* __ASM_MACH_LOONGSON1_REGS_PWM_H */
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