Akshu Agrawal a1b1e9880f ASoC: AMD: Change MCLK to 48Mhz ... 25Mhz MCLK which was earlier used was of spread type. Thus, we were not getting accurate rate. The 48Mhz system clk is of non-spread type and we are changing to it to get accurate rate. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>		2018-08-28 20:51:25 +01:00
..
include	ASoC: AMD : add ACP 2.2 register headers	2016-01-10 12:44:10 +00:00
acp-da7219-max98357a.c	ASoC: AMD: Change MCLK to 48Mhz	2018-08-28 20:51:25 +01:00
acp-pcm-dma.c	ASoC: AMD: Set delay value for the capture case	2018-08-06 17:02:09 +01:00
acp-rt5645.c	ASoC: rt5645/rt5677: replace codec to component	2018-02-12 11:18:44 +00:00
acp.h	ASoC: AMD: Modified DMA pointer for capture	2018-08-06 17:02:09 +01:00
Kconfig	ASoC: AMD: Add a fix voltage regulator for DA7219 and ADAU7002	2018-07-26 14:07:47 +01:00
Makefile	ASoC: AMD: Add machine driver for ST DA7219 MAX98357	2018-02-16 16:03:46 +00:00