Geert Uytterhoeven 8e1c3aa30c arm64: dts: r8a7795: Add CA53 L2 cache-controller node ... Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>		2016-02-17 14:53:14 +09:00
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dts	arm64: dts: r8a7795: Add CA53 L2 cache-controller node	2016-02-17 14:53:14 +09:00
.gitignore	arm64: Build infrastructure	2012-09-17 13:42:21 +01:00
install.sh	arm64: Build infrastructure	2012-09-17 13:42:21 +01:00
Makefile	arm64: enable more compressed Image formats	2015-07-27 11:08:39 +01:00