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983d308cb8
An interesting bug occurs on Pineview through which the root cause is that the writes of the PTE values into the GTT is not serialised with subsequent memory access through the GTT (when using WC updates of the PTE values). This is despite there being a posting read after the GTT update. However, by changing the address of the posting read, the memory access is indeed serialised correctly. Whilst we are manipulating the memory barriers, we can remove the compiler :memory restraint on the intermediate PTE writes knowing that we explicitly perform a posting read afterwards. v2: Replace posting reads with explicit write memory barriers - in particular this is advantages in case of single page objects. Update comments to mention this issue is only with WC writes. Testcase: igt/gem_exec_big #pnv Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88191 Tested-by: huax.lu@intel.com (v1) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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| .. | ||
| agp.h | ||
| ali-agp.c | ||
| alpha-agp.c | ||
| amd64-agp.c | ||
| amd-k7-agp.c | ||
| ati-agp.c | ||
| backend.c | ||
| compat_ioctl.c | ||
| compat_ioctl.h | ||
| efficeon-agp.c | ||
| frontend.c | ||
| generic.c | ||
| hp-agp.c | ||
| i460-agp.c | ||
| intel-agp.c | ||
| intel-agp.h | ||
| intel-gtt.c | ||
| isoch.c | ||
| Kconfig | ||
| Makefile | ||
| nvidia-agp.c | ||
| parisc-agp.c | ||
| sgi-agp.c | ||
| sis-agp.c | ||
| sworks-agp.c | ||
| uninorth-agp.c | ||
| via-agp.c | ||