mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 00:22:07 +07:00
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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/*
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* Write back the dirty D-caches, but not invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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static void sh4__flush_wback_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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__ocbwb(v); v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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__ocbwb(v); v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* Write back the dirty D-caches and invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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static void sh4__flush_purge_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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__ocbp(v); v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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__ocbp(v); v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* No write back please
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*/
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static void sh4__flush_invalidate_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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__ocbi(v); v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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__ocbi(v); v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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void __init sh4__flush_region_init(void)
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{
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__flush_wback_region = sh4__flush_wback_region;
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__flush_invalidate_region = sh4__flush_invalidate_region;
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__flush_purge_region = sh4__flush_purge_region;
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}
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