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d298e6a27a
Configure the display Quality of service (QoS) levels priority if the optional property node "arm,malidp-aqros-value" is defined in DTS file. QoS signaling using AQROS and AWQOS AXI interface signals, the AQROS is driven from the "RQOS" register, so needed to program the RQOS register to avoid the high resolutions flicker issue on the LS1028A platform. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190910075913.17650-2-wen.he_1@nxp.com
302 lines
11 KiB
C
302 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* ARM Mali DP500/DP550/DP650 registers definition.
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*/
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#ifndef __MALIDP_REGS_H__
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#define __MALIDP_REGS_H__
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/*
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* abbreviations used:
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* - DC - display core (general settings)
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* - DE - display engine
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* - SE - scaling engine
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*/
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/* interrupt bit masks */
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#define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
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#define MALIDP500_DE_IRQ_AXI_ERR (1 << 4)
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#define MALIDP500_DE_IRQ_VSYNC (1 << 5)
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#define MALIDP500_DE_IRQ_PROG_LINE (1 << 6)
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#define MALIDP500_DE_IRQ_SATURATION (1 << 7)
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#define MALIDP500_DE_IRQ_CONF_VALID (1 << 8)
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#define MALIDP500_DE_IRQ_CONF_MODE (1 << 11)
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#define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17)
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#define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18)
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#define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19)
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#define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24)
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#define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28)
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#define MALIDP500_DE_IRQ_GLOBAL (1 << 31)
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#define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
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#define MALIDP500_SE_IRQ_CONF_VALID (1 << 4)
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#define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5)
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#define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8)
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#define MALIDP500_SE_IRQ_OVERRUN (1 << 9)
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#define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12)
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#define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13)
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#define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17)
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#define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18)
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#define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28)
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#define MALIDP500_SE_IRQ_GLOBAL (1 << 31)
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#define MALIDP550_DE_IRQ_SATURATION (1 << 8)
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#define MALIDP550_DE_IRQ_VSYNC (1 << 12)
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#define MALIDP550_DE_IRQ_PROG_LINE (1 << 13)
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#define MALIDP550_DE_IRQ_AXI_ERR (1 << 16)
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#define MALIDP550_SE_IRQ_EOW (1 << 0)
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#define MALIDP550_SE_IRQ_AXI_ERR (1 << 16)
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#define MALIDP550_SE_IRQ_OVR (1 << 17)
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#define MALIDP550_SE_IRQ_IBSY (1 << 18)
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#define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
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#define MALIDP550_DC_IRQ_CONF_MODE (1 << 4)
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#define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16)
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#define MALIDP550_DC_IRQ_DE (1 << 20)
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#define MALIDP550_DC_IRQ_SE (1 << 24)
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#define MALIDP650_DE_IRQ_DRIFT (1 << 4)
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#define MALIDP650_DE_IRQ_ACEV1 (1 << 17)
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#define MALIDP650_DE_IRQ_ACEV2 (1 << 18)
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#define MALIDP650_DE_IRQ_ACEG (1 << 19)
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#define MALIDP650_DE_IRQ_AXIEP (1 << 28)
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/* bit masks that are common between products */
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#define MALIDP_CFG_VALID (1 << 0)
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#define MALIDP_DISP_FUNC_GAMMA (1 << 0)
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#define MALIDP_DISP_FUNC_CADJ (1 << 4)
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#define MALIDP_DISP_FUNC_ILACED (1 << 8)
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#define MALIDP_SCALE_ENGINE_EN (1 << 16)
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#define MALIDP_SE_MEMWRITE_EN (2 << 5)
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/* register offsets for IRQ management */
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#define MALIDP_REG_STATUS 0x00000
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#define MALIDP_REG_SETIRQ 0x00004
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#define MALIDP_REG_MASKIRQ 0x00008
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#define MALIDP_REG_CLEARIRQ 0x0000c
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/* register offsets */
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#define MALIDP_DE_CORE_ID 0x00018
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#define MALIDP_DE_DISPLAY_FUNC 0x00020
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/* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
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#define MALIDP_DE_H_TIMINGS 0x0
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#define MALIDP_DE_V_TIMINGS 0x4
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#define MALIDP_DE_SYNC_WIDTH 0x8
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#define MALIDP_DE_HV_ACTIVE 0xc
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/* Stride register offsets relative to Lx_BASE */
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#define MALIDP_DE_LG_STRIDE 0x18
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#define MALIDP_DE_LV_STRIDE0 0x18
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#define MALIDP550_DE_LS_R1_STRIDE 0x28
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/* macros to set values into registers */
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#define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0)
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#define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16)
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#define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0)
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#define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0)
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#define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16)
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#define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0)
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#define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16)
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#define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0)
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#define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16)
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#define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16)
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/* register offsets relative to MALIDP5x0_COEFFS_BASE */
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#define MALIDP_COLOR_ADJ_COEF 0x00000
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#define MALIDP_COEF_TABLE_ADDR 0x00030
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#define MALIDP_COEF_TABLE_DATA 0x00034
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/* Scaling engine registers and masks. */
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#define MALIDP_SE_SCALING_EN (1 << 0)
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#define MALIDP_SE_ALPHA_EN (1 << 1)
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#define MALIDP_SE_ENH_MASK 3
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#define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2)
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#define MALIDP_SE_RGBO_IF_EN (1 << 4)
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#define MALIDP550_SE_CTL_SEL_MASK 7
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#define MALIDP550_SE_CTL_VCSEL(x) \
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(((x) & MALIDP550_SE_CTL_SEL_MASK) << 20)
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#define MALIDP550_SE_CTL_HCSEL(x) \
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(((x) & MALIDP550_SE_CTL_SEL_MASK) << 16)
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/* Blocks with offsets from SE_CONTROL register. */
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#define MALIDP_SE_LAYER_CONTROL 0x14
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#define MALIDP_SE_L0_IN_SIZE 0x00
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#define MALIDP_SE_L0_OUT_SIZE 0x04
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#define MALIDP_SE_SET_V_SIZE(x) (((x) & 0x1fff) << 16)
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#define MALIDP_SE_SET_H_SIZE(x) (((x) & 0x1fff) << 0)
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#define MALIDP_SE_SCALING_CONTROL 0x24
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#define MALIDP_SE_H_INIT_PH 0x00
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#define MALIDP_SE_H_DELTA_PH 0x04
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#define MALIDP_SE_V_INIT_PH 0x08
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#define MALIDP_SE_V_DELTA_PH 0x0c
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#define MALIDP_SE_COEFFTAB_ADDR 0x10
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#define MALIDP_SE_COEFFTAB_ADDR_MASK 0x7f
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#define MALIDP_SE_V_COEFFTAB (1 << 8)
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#define MALIDP_SE_H_COEFFTAB (1 << 9)
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#define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \
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(MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
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#define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \
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(MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
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#define MALIDP_SE_COEFFTAB_DATA 0x14
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#define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff
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#define MALIDP_SE_SET_COEFFTAB_DATA(x) \
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((x) & MALIDP_SE_COEFFTAB_DATA_MASK)
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/* Enhance coeffents reigster offset */
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#define MALIDP_SE_IMAGE_ENH 0x3C
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/* ENH_LIMITS offset 0x0 */
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#define MALIDP_SE_ENH_LOW_LEVEL 24
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#define MALIDP_SE_ENH_HIGH_LEVEL 63
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#define MALIDP_SE_ENH_LIMIT_MASK 0xfff
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#define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \
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((x) & MALIDP_SE_ENH_LIMIT_MASK)
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#define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \
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(((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16)
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#define MALIDP_SE_ENH_COEFF0 0x04
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/* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */
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#define MALIDP_MW_FORMAT 0x00000
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#define MALIDP_MW_P1_STRIDE 0x00004
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#define MALIDP_MW_P2_STRIDE 0x00008
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#define MALIDP_MW_P1_PTR_LOW 0x0000c
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#define MALIDP_MW_P1_PTR_HIGH 0x00010
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#define MALIDP_MW_P2_PTR_LOW 0x0002c
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#define MALIDP_MW_P2_PTR_HIGH 0x00030
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/* register offsets and bits specific to DP500 */
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#define MALIDP500_ADDR_SPACE_SIZE 0x01000
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#define MALIDP500_DC_BASE 0x00000
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#define MALIDP500_DC_CONTROL 0x0000c
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#define MALIDP500_DC_CONFIG_REQ (1 << 17)
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#define MALIDP500_HSYNCPOL (1 << 20)
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#define MALIDP500_VSYNCPOL (1 << 21)
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#define MALIDP500_DC_CLEAR_MASK 0x300fff
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#define MALIDP500_DE_LINE_COUNTER 0x00010
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#define MALIDP500_DE_AXI_CONTROL 0x00014
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#define MALIDP500_DE_SECURE_CTRL 0x0001c
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#define MALIDP500_DE_CHROMA_KEY 0x00024
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#define MALIDP500_TIMINGS_BASE 0x00028
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#define MALIDP500_CONFIG_3D 0x00038
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#define MALIDP500_BGND_COLOR 0x0003c
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#define MALIDP500_OUTPUT_DEPTH 0x00044
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#define MALIDP500_COEFFS_BASE 0x00078
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/*
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* The YUV2RGB coefficients on the DP500 are not in the video layer's register
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* block. They belong in a separate block above the layer's registers, hence
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* the negative offset.
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*/
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#define MALIDP500_LV_YUV2RGB ((s16)(-0xB8))
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#define MALIDP500_DE_LV_BASE 0x00100
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#define MALIDP500_DE_LV_PTR_BASE 0x00124
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#define MALIDP500_DE_LV_AD_CTRL 0x00400
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#define MALIDP500_DE_LG1_BASE 0x00200
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#define MALIDP500_DE_LG1_PTR_BASE 0x0021c
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#define MALIDP500_DE_LG1_AD_CTRL 0x0040c
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#define MALIDP500_DE_LG2_BASE 0x00300
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#define MALIDP500_DE_LG2_PTR_BASE 0x0031c
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#define MALIDP500_DE_LG2_AD_CTRL 0x00418
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#define MALIDP500_SE_BASE 0x00c00
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#define MALIDP500_SE_CONTROL 0x00c0c
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#define MALIDP500_SE_MEMWRITE_OUT_SIZE 0x00c2c
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#define MALIDP500_SE_RGB_YUV_COEFFS 0x00C74
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#define MALIDP500_SE_MEMWRITE_BASE 0x00e00
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#define MALIDP500_DC_IRQ_BASE 0x00f00
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#define MALIDP500_CONFIG_VALID 0x00f00
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#define MALIDP500_CONFIG_ID 0x00fd4
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/*
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* The quality of service (QoS) register on the DP500. RQOS register values
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* are driven by the ARQOS signal, using AXI transacations, dependent on the
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* FIFO input level.
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* The RQOS register can also set QoS levels for:
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* - RED_ARQOS @ A 4-bit signal value for close to underflow conditions
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* - GREEN_ARQOS @ A 4-bit signal value for normal conditions
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*/
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#define MALIDP500_RQOS_QUALITY 0x00500
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/* register offsets and bits specific to DP550/DP650 */
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#define MALIDP550_ADDR_SPACE_SIZE 0x10000
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#define MALIDP550_DE_CONTROL 0x00010
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#define MALIDP550_DE_LINE_COUNTER 0x00014
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#define MALIDP550_DE_AXI_CONTROL 0x00018
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#define MALIDP550_DE_QOS 0x0001c
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#define MALIDP550_TIMINGS_BASE 0x00030
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#define MALIDP550_HSYNCPOL (1 << 12)
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#define MALIDP550_VSYNCPOL (1 << 28)
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#define MALIDP550_DE_DISP_SIDEBAND 0x00040
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#define MALIDP550_DE_BGND_COLOR 0x00044
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#define MALIDP550_DE_OUTPUT_DEPTH 0x0004c
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#define MALIDP550_COEFFS_BASE 0x00050
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#define MALIDP550_LV_YUV2RGB 0x00084
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#define MALIDP550_DE_LV1_BASE 0x00100
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#define MALIDP550_DE_LV1_PTR_BASE 0x00124
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#define MALIDP550_DE_LV1_AD_CTRL 0x001B8
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#define MALIDP550_DE_LV2_BASE 0x00200
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#define MALIDP550_DE_LV2_PTR_BASE 0x00224
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#define MALIDP550_DE_LV2_AD_CTRL 0x002B8
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#define MALIDP550_DE_LG_BASE 0x00300
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#define MALIDP550_DE_LG_PTR_BASE 0x0031c
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#define MALIDP550_DE_LG_AD_CTRL 0x00330
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#define MALIDP550_DE_LS_BASE 0x00400
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#define MALIDP550_DE_LS_PTR_BASE 0x0042c
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#define MALIDP550_DE_PERF_BASE 0x00500
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#define MALIDP550_SE_BASE 0x08000
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#define MALIDP550_SE_CONTROL 0x08010
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#define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7)
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#define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030
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#define MALIDP550_SE_RGB_YUV_COEFFS 0x08078
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#define MALIDP550_SE_MEMWRITE_BASE 0x08100
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#define MALIDP550_DC_BASE 0x0c000
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#define MALIDP550_DC_CONTROL 0x0c010
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#define MALIDP550_DC_CONFIG_REQ (1 << 16)
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#define MALIDP550_CONFIG_VALID 0x0c014
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#define MALIDP550_CONFIG_ID 0x0ffd4
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/* register offsets specific to DP650 */
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#define MALIDP650_DE_LV_MMU_CTRL 0x000D0
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#define MALIDP650_DE_LG_MMU_CTRL 0x00048
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#define MALIDP650_DE_LS_MMU_CTRL 0x00078
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/* bit masks to set the MMU control register */
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#define MALIDP_MMU_CTRL_EN (1 << 0)
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#define MALIDP_MMU_CTRL_MODE (1 << 4)
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#define MALIDP_MMU_CTRL_PX_PS(x) (1 << (8 + (x)))
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#define MALIDP_MMU_CTRL_PP_NUM_REQ(x) (((x) & 0x7f) << 12)
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/* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */
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/* The following register offsets are common for DP500, DP550 and DP650 */
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#define MALIDP_AD_CROP_H 0x4
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#define MALIDP_AD_CROP_V 0x8
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#define MALIDP_AD_END_PTR_LOW 0xc
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#define MALIDP_AD_END_PTR_HIGH 0x10
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/* AFBC decoder Registers */
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#define MALIDP_AD_EN BIT(0)
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#define MALIDP_AD_YTR BIT(4)
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#define MALIDP_AD_BS BIT(8)
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#define MALIDP_AD_CROP_RIGHT_OFFSET 16
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#define MALIDP_AD_CROP_BOTTOM_OFFSET 16
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/*
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* Starting with DP550 the register map blocks has been standardised to the
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* following layout:
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*
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* Offset Block registers
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* 0x00000 Display Engine
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* 0x08000 Scaling Engine
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* 0x0c000 Display Core
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* 0x10000 Secure control
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*
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* The old DP500 IP mixes some DC with the DE registers, hence the need
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* for a mapping structure.
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*/
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#endif /* __MALIDP_REGS_H__ */
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