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8ce877a8eb
The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
84 lines
3.3 KiB
C
84 lines
3.3 KiB
C
/****************************************************************************/
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/*
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* m52xxacr.h -- ColdFire version 2 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m52xxacr_h
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#define m52xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 2 cores have a similar
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* cache setup. Although not absolutely identical the cache register
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* definitions are compatible for all of them. Mostly they support a
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* configurable cache memory that can be instruction only, data only,
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* or split instruction and data. The exception is the very old version 2
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* core based parts, like the 5206(e), 5249 and 5272, which are instruction
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* cache only. Cache size varies from 2k up to 16k.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_CENB 0x80000000 /* Enable cache */
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#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
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#define CACR_CINV 0x01000000 /* Invalidate cache */
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#define CACR_DISI 0x00800000 /* Disable instruction cache */
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#define CACR_DISD 0x00400000 /* Disable data cache */
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#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
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#define CACR_INVD 0x00100000 /* Invalidate data cache */
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#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
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#define CACR_DCM 0x00000200 /* Default cache mode */
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#define CACR_DBWE 0x00000100 /* Buffered write enable */
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#define CACR_DWP 0x00000020 /* Write protection */
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#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CENB 0x00000000 /* Caching of region enabled */
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#define ACR_CDIS 0x00000040 /* Caching of region disabled */
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#define ACR_BWE 0x00000020 /* Write buffer enabled */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/*
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* Set the cache controller settings we will use. This code is set to
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* only use the instruction cache, even on the controllers that support
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* split cache. (This setup is trying to preserve the existing behavior
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* for now, in the furture I hope to actually use the split cache mode).
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5249) || defined(CONFIG_M5272)
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#define CACHE_INIT (CACR_CINV)
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#define CACHE_MODE (CACR_CENB + CACR_DCM)
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#else
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#ifdef CONFIG_COLDFIRE_SW_A7
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#define CACHE_INIT (CACR_CINV + CACR_DISD)
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#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM)
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#else
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#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP)
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#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
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#endif
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#endif
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#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
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#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
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(0x000f0000) + \
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(ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
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#define ACR1_MODE 0
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/****************************************************************************/
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#endif /* m52xxsim_h */
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