mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 19:56:51 +07:00
d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
*
|
|
* Parts of this file are based on Ralink's 2.6.21 BSP
|
|
*
|
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
|
* Copyright (C) 2013 John Crispin <john@phrozen.org>
|
|
*/
|
|
|
|
#ifndef _RT288X_REGS_H_
|
|
#define _RT288X_REGS_H_
|
|
|
|
#define RT2880_SYSC_BASE 0x00300000
|
|
|
|
#define SYSC_REG_CHIP_NAME0 0x00
|
|
#define SYSC_REG_CHIP_NAME1 0x04
|
|
#define SYSC_REG_CHIP_ID 0x0c
|
|
#define SYSC_REG_SYSTEM_CONFIG 0x10
|
|
#define SYSC_REG_CLKCFG 0x30
|
|
|
|
#define RT2880_CHIP_NAME0 0x38325452
|
|
#define RT2880_CHIP_NAME1 0x20203038
|
|
|
|
#define CHIP_ID_ID_MASK 0xff
|
|
#define CHIP_ID_ID_SHIFT 8
|
|
#define CHIP_ID_REV_MASK 0xff
|
|
|
|
#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
|
|
#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
|
|
#define SYSTEM_CONFIG_CPUCLK_250 0x0
|
|
#define SYSTEM_CONFIG_CPUCLK_266 0x1
|
|
#define SYSTEM_CONFIG_CPUCLK_280 0x2
|
|
#define SYSTEM_CONFIG_CPUCLK_300 0x3
|
|
|
|
#define RT2880_GPIO_MODE_I2C BIT(0)
|
|
#define RT2880_GPIO_MODE_UART0 BIT(1)
|
|
#define RT2880_GPIO_MODE_SPI BIT(2)
|
|
#define RT2880_GPIO_MODE_UART1 BIT(3)
|
|
#define RT2880_GPIO_MODE_JTAG BIT(4)
|
|
#define RT2880_GPIO_MODE_MDIO BIT(5)
|
|
#define RT2880_GPIO_MODE_SDRAM BIT(6)
|
|
#define RT2880_GPIO_MODE_PCI BIT(7)
|
|
|
|
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
|
|
|
|
#define RT2880_SDRAM_BASE 0x08000000
|
|
#define RT2880_MEM_SIZE_MIN 2
|
|
#define RT2880_MEM_SIZE_MAX 128
|
|
|
|
#endif
|