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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f490682a6b
The width of HT-bus is only 40-bit, but Loongson-3 has 48-bit physical address. This implies only node-0's memory is DMAable because high bits (Node ID) will lost. Fortunately, by configuring address windows in firmware, we can extract 2bit Node ID (bit 44~47, only bit 44~45 used now) from Loongson-3's 48-bit address space and embed it into 40-bit (bit 37~38). Every NUMA node can do DMA now (however, maximum memory of each node is reduced to 2^37 = 128GB). Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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*/
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#ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H
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#define __ASM_MACH_LOONGSON_DMA_COHERENCE_H
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#ifdef CONFIG_SWIOTLB
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#include <linux/swiotlb.h>
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#endif
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struct device;
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extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
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extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
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static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
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size_t size)
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{
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#ifdef CONFIG_CPU_LOONGSON3
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return phys_to_dma(dev, virt_to_phys(addr));
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#else
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return virt_to_phys(addr) | 0x80000000;
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#endif
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}
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static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
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struct page *page)
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{
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#ifdef CONFIG_CPU_LOONGSON3
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return phys_to_dma(dev, page_to_phys(page));
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#else
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return page_to_phys(page) | 0x80000000;
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#endif
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}
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static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
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dma_addr_t dma_addr)
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{
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#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
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return dma_to_phys(dev, dma_addr);
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#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
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#else
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return dma_addr & 0x7fffffff;
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#endif
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}
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static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction)
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{
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}
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static inline int plat_dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if (mask < DMA_BIT_MASK(24))
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return 0;
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return 1;
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}
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static inline int plat_device_is_coherent(struct device *dev)
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{
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#ifdef CONFIG_DMA_NONCOHERENT
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return 0;
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#else
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return 1;
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#endif /* CONFIG_DMA_NONCOHERENT */
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}
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#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
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