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cfcbc2dbb7
The secure clocks on omap4 are similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table 3-1346 L4PER_CM2 Registers Mapping Summary". The secure clocks are part of the l4_per clock manager. As the l4_per clock manager has now two clock domains as children, let's also update the l4_per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
150 lines
6.0 KiB
C
150 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2017 Texas Instruments, Inc.
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*/
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#ifndef __DT_BINDINGS_CLK_OMAP4_H
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#define __DT_BINDINGS_CLK_OMAP4_H
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#define OMAP4_CLKCTRL_OFFSET 0x20
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#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
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/* mpuss clocks */
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#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* tesla clocks */
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#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* abe clocks */
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#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
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#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
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#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
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#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
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#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
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#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
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#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
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#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
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#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
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#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
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/* l4_ao clocks */
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#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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/* l3_1 clocks */
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#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l3_2 clocks */
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#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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/* ducati clocks */
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#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l3_dma clocks */
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#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l3_emif clocks */
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#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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/* d2d clocks */
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#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l4_cfg clocks */
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#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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/* l3_instr clocks */
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#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
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/* ivahd clocks */
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#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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/* iss clocks */
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#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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/* l3_dss clocks */
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#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l3_gfx clocks */
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#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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/* l3_init clocks */
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#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
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#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
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#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
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#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
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#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
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/* l4_per clocks */
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#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
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#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
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#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
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#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
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#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
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#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
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#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
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#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
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#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
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#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
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#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
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#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
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#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
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#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
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#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
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#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
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#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
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#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
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#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
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#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
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#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
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#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
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#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
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#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
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#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
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#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
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#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
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#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
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/* l4_secure clocks */
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#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
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#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
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#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
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#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
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#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
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#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
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#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
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#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
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#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
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/* l4_wkup clocks */
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#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
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#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
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#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
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#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
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#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
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/* emu_sys clocks */
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#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
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#endif
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