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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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281b05392f
These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUAT24+62CrR//JCVInAQLQBQ/8ClDSFYKTkh3XuzryyO3xkiuuj9wp3/av oEzro6HmSFDeWlqyQYYM9nKn6n3zFyyumG7oHt3OyRwrtV742rMOpTK+/Ntj2lFB xUVwKQfu2gEMHvwca3VoXia/pX7knvedEf9bNjeCznkKxQCKCArK2821/2UDGhwx L3/lD70AhpfK0DInNr6HusnZG2pzCdV1tLXUvgs08I68wL7Ps1TDPOLLyTo9dAgf k+E1cpRNLahyiVUBfnp+n3Dg0T+/7iD6zrR7bE9i/zhv6XUcLPt2K5XqYnPuQvzK sHIG8zROmNWzaIzgwYVpJAofi0SHq1OjvA7RtepOq/pGe5QvB9y1RISlpwzBr6Fh 4yuBkeN/Azk0xSHw5w++8L4y/oSSNhB9OWgIZGChZMW33bnHyiZW9mDFJ/PyWD0F kRl++tTuQqDvT5Wx4DXX8RGekIiFq48+MMx3yJjuGarmVsPEvShQCf8TkBbl/KQY /AEXMJTaVTED0R/q+NOY/r4oMFC4JtAVo1ZtTga+N5cYWQCwI9HVSgAKw84Yc1Hj h9r7XjDhmGYFWMfWe9V5NtFNmXl6tAo66fMzSG6+9k+UEXiF1WrhnzBuks5zFU7z z4WBRL0GmaNBdq58dJoM4lucnuhhQk2m7wz5Lt4o17enw0dAfSXQMstDMnbE7c51 65yZh8o9mxs= =WdYR -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
497 lines
11 KiB
C
497 lines
11 KiB
C
/*
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* linux/arch/arm/mach-omap2/io.c
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*
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* OMAP2 I/O mapping code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Copyright (C) 2007-2009 Texas Instruments
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*
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* Author:
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* Juha Yrjola <juha.yrjola@nokia.com>
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* Syed Khasim <x0khasim@ti.com>
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*
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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#include <plat/sram.h>
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#include <plat/sdrc.h>
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#include <plat/serial.h>
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#include <plat/omap-pm.h>
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#include <plat/omap_hwmod.h>
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#include <plat/multi.h>
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#include "iomap.h"
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#include "voltage.h"
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "common.h"
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#include "clock2xxx.h"
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#include "clock3xxx.h"
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#include "clock44xx.h"
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
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static struct map_desc omap24xx_io_desc[] __initdata = {
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{
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.virtual = L3_24XX_VIRT,
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.pfn = __phys_to_pfn(L3_24XX_PHYS),
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.length = L3_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_24XX_VIRT,
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.pfn = __phys_to_pfn(L4_24XX_PHYS),
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.length = L4_24XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#ifdef CONFIG_SOC_OMAP2420
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static struct map_desc omap242x_io_desc[] __initdata = {
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{
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.virtual = DSP_MEM_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
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.length = DSP_MEM_2420_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_IPI_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
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.length = DSP_IPI_2420_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_MMU_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
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.length = DSP_MMU_2420_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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static struct map_desc omap243x_io_desc[] __initdata = {
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{
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.virtual = L4_WK_243X_VIRT,
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.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
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.length = L4_WK_243X_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
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.length = OMAP243X_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
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.length = OMAP243X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
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.length = OMAP243X_SMS_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct map_desc omap34xx_io_desc[] __initdata = {
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{
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.virtual = L3_34XX_VIRT,
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.pfn = __phys_to_pfn(L3_34XX_PHYS),
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.length = L3_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP34XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
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.length = OMAP34XX_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
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.length = OMAP343X_SMS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
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.length = OMAP343X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_PER_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
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.length = L4_PER_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_EMU_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
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.length = L4_EMU_34XX_SIZE,
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.type = MT_DEVICE
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},
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#if defined(CONFIG_DEBUG_LL) && \
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(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
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{
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.virtual = ZOOM_UART_VIRT,
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.pfn = __phys_to_pfn(ZOOM_UART_BASE),
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.length = SZ_1M,
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.type = MT_DEVICE
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},
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#endif
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};
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#endif
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#ifdef CONFIG_SOC_OMAPTI81XX
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static struct map_desc omapti81xx_io_desc[] __initdata = {
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#ifdef CONFIG_SOC_OMAPAM33XX
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static struct map_desc omapam33xx_io_desc[] __initdata = {
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_WK_AM33XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
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.length = L4_WK_AM33XX_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static struct map_desc omap44xx_io_desc[] __initdata = {
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{
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.virtual = L3_44XX_VIRT,
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.pfn = __phys_to_pfn(L3_44XX_PHYS),
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.length = L3_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_44XX_PHYS),
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.length = L4_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
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.length = OMAP44XX_GPMC_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_EMIF1_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
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.length = OMAP44XX_EMIF1_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_EMIF2_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
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.length = OMAP44XX_EMIF2_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_DMM_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
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.length = OMAP44XX_DMM_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
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.length = L4_PER_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_EMU_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
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.length = L4_EMU_44XX_SIZE,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_OMAP4_ERRATA_I688
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{
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.virtual = OMAP4_SRAM_VA,
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.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
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.length = PAGE_SIZE,
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.type = MT_MEMORY_SO,
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},
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#endif
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};
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#endif
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#ifdef CONFIG_SOC_OMAP2420
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void __init omap242x_map_common_io(void)
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{
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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void __init omap243x_map_common_io(void)
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{
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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void __init omap34xx_map_common_io(void)
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{
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iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_OMAPTI81XX
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void __init omapti81xx_map_common_io(void)
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{
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iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_OMAPAM33XX
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void __init omapam33xx_map_common_io(void)
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{
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iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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void __init omap44xx_map_common_io(void)
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{
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iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
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omap_barriers_init();
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}
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#endif
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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* Sets the CORE DPLL3 M2 divider to the same value that it's at
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* currently. This has the effect of setting the SDRC SDRAM AC timing
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* registers to the values currently defined by the kernel. Currently
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* only defined for OMAP3; will return 0 if called on OMAP2. Returns
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* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
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* or passes along the return value of clk_set_rate().
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*/
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static int __init _omap2_init_reprogram_sdrc(void)
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{
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struct clk *dpll3_m2_ck;
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int v = -EINVAL;
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long rate;
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if (!cpu_is_omap34xx())
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return 0;
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dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
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if (IS_ERR(dpll3_m2_ck))
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return -EINVAL;
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rate = clk_get_rate(dpll3_m2_ck);
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pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
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v = clk_set_rate(dpll3_m2_ck, rate);
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if (v)
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pr_err("dpll3_m2_clk rate change failed: %d\n", v);
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clk_put(dpll3_m2_ck);
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return v;
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}
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static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
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{
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return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
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}
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static void __init omap_common_init_early(void)
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{
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omap_init_consistent_dma_size();
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}
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static void __init omap_hwmod_init_postsetup(void)
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{
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u8 postsetup_state;
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/* Set the default postsetup state for all hwmods */
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#ifdef CONFIG_PM_RUNTIME
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postsetup_state = _HWMOD_STATE_IDLE;
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#else
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postsetup_state = _HWMOD_STATE_ENABLED;
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#endif
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omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
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/*
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* Set the default postsetup state for unusual modules (like
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* MPU WDT).
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*
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* The postsetup_state is not actually used until
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* omap_hwmod_late_init(), so boards that desire full watchdog
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* coverage of kernel initialization can reprogram the
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* postsetup_state between the calls to
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* omap2_init_common_infra() and omap_sdrc_init().
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*
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* XXX ideally we could detect whether the MPU WDT was currently
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* enabled here and make this conditional
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*/
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postsetup_state = _HWMOD_STATE_DISABLED;
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omap_hwmod_for_each_by_class("wd_timer",
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_set_hwmod_postsetup_state,
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&postsetup_state);
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omap_pm_if_early_init();
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}
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#ifdef CONFIG_SOC_OMAP2420
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void __init omap2420_init_early(void)
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{
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omap2_set_globals_242x();
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omap2xxx_check_revision();
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omap_common_init_early();
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omap2xxx_voltagedomains_init();
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omap242x_powerdomains_init();
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omap242x_clockdomains_init();
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omap2420_hwmod_init();
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omap_hwmod_init_postsetup();
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omap2420_clk_init();
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}
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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void __init omap2430_init_early(void)
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{
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omap2_set_globals_243x();
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omap2xxx_check_revision();
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omap_common_init_early();
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omap2xxx_voltagedomains_init();
|
|
omap243x_powerdomains_init();
|
|
omap243x_clockdomains_init();
|
|
omap2430_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap2430_clk_init();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Currently only board-omap3beagle.c should call this because of the
|
|
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
|
|
*/
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap3_init_early(void)
|
|
{
|
|
omap2_set_globals_3xxx();
|
|
omap3xxx_check_revision();
|
|
omap3xxx_check_features();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
|
|
void __init omap3430_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap3630_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init am35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init ti81xx_init_early(void)
|
|
{
|
|
omap2_set_globals_ti81xx();
|
|
omap3xxx_check_revision();
|
|
ti81xx_check_features();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap4430_init_early(void)
|
|
{
|
|
omap2_set_globals_443x();
|
|
omap4xxx_check_revision();
|
|
omap4xxx_check_features();
|
|
omap_common_init_early();
|
|
omap44xx_voltagedomains_init();
|
|
omap44xx_powerdomains_init();
|
|
omap44xx_clockdomains_init();
|
|
omap44xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap4xxx_clk_init();
|
|
}
|
|
#endif
|
|
|
|
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
|
struct omap_sdrc_params *sdrc_cs1)
|
|
{
|
|
omap_sram_init();
|
|
|
|
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
|
_omap2_init_reprogram_sdrc();
|
|
}
|
|
}
|