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f384796c40
For addresses above 512TB we allocate additional mmu contexts. To make
it all easy, addresses above 512TB are handled with IR/DR=1 and with
stack frame setup.
The mmu_context_t is also updated to track the new extended_ids. To
support upto 4PB we need a total 8 contexts.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[mpe: Minor formatting tweaks and comment wording, switch BUG to WARN
in get_ea_context().]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
335 lines
9.6 KiB
ArmAsm
335 lines
9.6 KiB
ArmAsm
/*
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* Low-level SLB routines
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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*
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* Based on earlier C version:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/firmware.h>
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/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register containing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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* rf = flags
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*
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* - rt and rx must be different registers
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* - The answer will end up in the low VSID_BITS bits of rt. The higher
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* bits may contain other garbage, so you may need to mask the
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* result.
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*/
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#define ASM_VSID_SCRAMBLE(rt, rx, rf, size) \
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lis rx,VSID_MULTIPLIER_##size@h; \
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ori rx,rx,VSID_MULTIPLIER_##size@l; \
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mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
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/* \
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* powermac get slb fault before feature fixup, so make 65 bit part \
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* the default part of feature fixup \
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*/ \
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BEGIN_MMU_FTR_SECTION \
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srdi rx,rt,VSID_BITS_65_##size; \
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clrldi rt,rt,(64-VSID_BITS_65_##size); \
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add rt,rt,rx; \
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addi rx,rt,1; \
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srdi rx,rx,VSID_BITS_65_##size; \
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add rt,rt,rx; \
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rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_65_##size)); \
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MMU_FTR_SECTION_ELSE \
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srdi rx,rt,VSID_BITS_##size; \
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clrldi rt,rt,(64-VSID_BITS_##size); \
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add rt,rt,rx; /* add high and low bits */ \
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addi rx,rt,1; \
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srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
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add rt,rt,rx; \
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rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_##size)); \
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
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/* void slb_allocate(unsigned long ea);
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*
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* Create an SLB entry for the given EA (user or kernel).
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* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* r3 is preserved.
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* No other registers are examined or changed.
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*/
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_GLOBAL(slb_allocate)
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/*
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* Check if the address falls within the range of the first context, or
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* if we may need to handle multi context. For the first context we
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* allocate the slb entry via the fast path below. For large address we
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* branch out to C-code and see if additional contexts have been
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* allocated.
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* The test here is:
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* (ea & ~REGION_MASK) >= (1ull << MAX_EA_BITS_PER_CONTEXT)
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*/
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rldicr. r9,r3,4,(63 - MAX_EA_BITS_PER_CONTEXT - 4)
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bne- 8f
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srdi r9,r3,60 /* get region */
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srdi r10,r3,SID_SHIFT /* get esid */
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cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
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/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
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blt cr7,0f /* user or kernel? */
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/* Check if hitting the linear mapping or some other kernel space
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*/
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bne cr7,1f
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/* Linear mapping encoding bits, the "li" instruction below will
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* be patched by the kernel at boot
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*/
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.globl slb_miss_kernel_load_linear
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slb_miss_kernel_load_linear:
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li r11,0
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/*
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* context = (ea >> 60) - (0xc - 1)
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* r9 = region id.
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*/
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subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
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BEGIN_FTR_SECTION
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b .Lslb_finish_load
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
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b .Lslb_finish_load_1T
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1:
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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cmpldi cr0,r9,0xf
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bne 1f
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/* Check virtual memmap region. To be patched at kernel boot */
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.globl slb_miss_kernel_load_vmemmap
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slb_miss_kernel_load_vmemmap:
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li r11,0
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b 6f
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1:
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#endif /* CONFIG_SPARSEMEM_VMEMMAP */
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/*
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* r10 contains the ESID, which is the original faulting EA shifted
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* right by 28 bits. We need to compare that with (H_VMALLOC_END >> 28)
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* which is 0xd00038000. That can't be used as an immediate, even if we
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* ignored the 0xd, so we have to load it into a register, and we only
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* have one register free. So we must load all of (H_VMALLOC_END >> 28)
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* into a register and compare ESID against that.
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*/
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lis r11,(H_VMALLOC_END >> 32)@h // r11 = 0xffffffffd0000000
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ori r11,r11,(H_VMALLOC_END >> 32)@l // r11 = 0xffffffffd0003800
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// Rotate left 4, then mask with 0xffffffff0
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rldic r11,r11,4,28 // r11 = 0xd00038000
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cmpld r10,r11 // if r10 >= r11
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bge 5f // goto io_mapping
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/*
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* vmalloc mapping gets the encoding from the PACA as the mapping
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* can be demoted from 64K -> 4K dynamically on some machines.
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*/
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lhz r11,PACAVMALLOCSLLP(r13)
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b 6f
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5:
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/* IO mapping */
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.globl slb_miss_kernel_load_io
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slb_miss_kernel_load_io:
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li r11,0
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6:
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/*
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* context = (ea >> 60) - (0xc - 1)
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* r9 = region id.
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*/
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subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
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BEGIN_FTR_SECTION
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b .Lslb_finish_load
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
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b .Lslb_finish_load_1T
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0: /*
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* For userspace addresses, make sure this is region 0.
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*/
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cmpdi r9, 0
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bne- 8f
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/*
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* user space make sure we are within the allowed limit
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*/
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ld r11,PACA_SLB_ADDR_LIMIT(r13)
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cmpld r3,r11
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bge- 8f
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/* when using slices, we extract the psize off the slice bitmaps
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* and then we need to get the sllp encoding off the mmu_psize_defs
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* array.
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*
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* XXX This is a bit inefficient especially for the normal case,
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* so we should try to implement a fast path for the standard page
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* size using the old sllp value so we avoid the array. We cannot
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* really do dynamic patching unfortunately as processes might flip
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* between 4k and 64k standard page size
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*/
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#ifdef CONFIG_PPC_MM_SLICES
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/* r10 have esid */
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cmpldi r10,16
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/* below SLICE_LOW_TOP */
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blt 5f
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/*
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* Handle hpsizes,
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* r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
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*/
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srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
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addi r9,r11,PACAHIGHSLICEPSIZE
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lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
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/* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
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rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
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b 6f
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5:
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/*
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* Handle lpsizes
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* r9 is get_paca()->context.low_slices_psize[index], r11 is mask_index
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*/
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srdi r11,r10,1 /* index */
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addi r9,r11,PACALOWSLICESPSIZE
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lbzx r9,r13,r9 /* r9 is lpsizes[r11] */
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rldicl r11,r10,0,63 /* r11 = r10 & 0x1 */
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6:
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sldi r11,r11,2 /* index * 4 */
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/* Extract the psize and multiply to get an array offset */
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srd r9,r9,r11
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andi. r9,r9,0xf
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mulli r9,r9,MMUPSIZEDEFSIZE
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/* Now get to the array and obtain the sllp
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*/
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ld r11,PACATOC(r13)
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ld r11,mmu_psize_defs@got(r11)
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add r11,r11,r9
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ld r11,MMUPSIZESLLP(r11)
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ori r11,r11,SLB_VSID_USER
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#else
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/* paca context sllp already contains the SLB_VSID_USER bits */
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lhz r11,PACACONTEXTSLLP(r13)
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#endif /* CONFIG_PPC_MM_SLICES */
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ld r9,PACACONTEXTID(r13)
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BEGIN_FTR_SECTION
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cmpldi r10,0x1000
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bge .Lslb_finish_load_1T
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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b .Lslb_finish_load
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8: /* invalid EA - return an error indication */
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crset 4*cr0+eq /* indicate failure */
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blr
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/*
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* Finish loading of an SLB entry and return
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*
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* r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
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*/
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.Lslb_finish_load:
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rldimi r10,r9,ESID_BITS,0
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ASM_VSID_SCRAMBLE(r10,r9,r11,256M)
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/* r3 = EA, r11 = VSID data */
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/*
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* Find a slot, round robin. Previously we tried to find a
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* free slot first but that took too long. Unfortunately we
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* dont have any LRU information to help us choose a slot.
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*/
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mr r9,r3
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/* slb_finish_load_1T continues here. r9=EA with non-ESID bits clear */
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7: ld r10,PACASTABRR(r13)
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addi r10,r10,1
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/* This gets soft patched on boot. */
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.globl slb_compare_rr_to_size
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slb_compare_rr_to_size:
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cmpldi r10,0
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blt+ 4f
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li r10,SLB_NUM_BOLTED
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4:
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std r10,PACASTABRR(r13)
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3:
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rldimi r9,r10,0,36 /* r9 = EA[0:35] | entry */
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oris r10,r9,SLB_ESID_V@h /* r10 = r9 | SLB_ESID_V */
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/* r9 = ESID data, r11 = VSID data */
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/*
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* No need for an isync before or after this slbmte. The exception
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* we enter with and the rfid we exit with are context synchronizing.
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*/
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slbmte r11,r10
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/* we're done for kernel addresses */
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crclr 4*cr0+eq /* set result to "success" */
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bgelr cr7
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/* Update the slb cache */
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lhz r9,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
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cmpldi r9,SLB_CACHE_ENTRIES
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bge 1f
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/* still room in the slb cache */
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sldi r11,r9,2 /* r11 = offset * sizeof(u32) */
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srdi r10,r10,28 /* get the 36 bits of the ESID */
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add r11,r11,r13 /* r11 = (u32 *)paca + offset */
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stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
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addi r9,r9,1 /* offset++ */
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b 2f
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1: /* offset >= SLB_CACHE_ENTRIES */
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li r9,SLB_CACHE_ENTRIES+1
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2:
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sth r9,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
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crclr 4*cr0+eq /* set result to "success" */
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blr
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/*
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* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
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*
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* r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
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*/
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.Lslb_finish_load_1T:
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srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
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rldimi r10,r9,ESID_BITS_1T,0
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ASM_VSID_SCRAMBLE(r10,r9,r11,1T)
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li r10,MMU_SEGSIZE_1T
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rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
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/* r3 = EA, r11 = VSID data */
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clrrdi r9,r3,SID_SHIFT_1T /* clear out non-ESID bits */
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b 7b
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_ASM_NOKPROBE_SYMBOL(slb_allocate)
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_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_linear)
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_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_io)
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_ASM_NOKPROBE_SYMBOL(slb_compare_rr_to_size)
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_vmemmap)
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#endif
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