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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8c27e6f305
Allow the timer register to be determined dynamically instead of at compile time. Use common virtual addresses for the registers across all MSM chips, and select the register mappings based on the detected CPU. Signed-off-by: David Brown <davidb@codeaurora.org>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* The MSM peripherals are spread all over across 768MB of physical
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* space, which makes just having a simple IO_ADDRESS macro to slide
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* them into the right virtual location rough. Instead, we will
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* provide a master phys->virt mapping for peripherals here.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IOMAP_H
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#define __ASM_ARCH_MSM_IOMAP_H
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#include <asm/sizes.h>
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/* Physical base address and size of peripherals.
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* Ordered by the virtual base addresses they will be mapped at.
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*
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* MSM_VIC_BASE must be an value that can be loaded via a "mov"
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* instruction, otherwise entry-macro.S will not compile.
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*
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* If you add or remove entries here, you'll want to edit the
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* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
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* changes.
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*
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*/
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#ifdef __ASSEMBLY__
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#define IOMEM(x) x
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#else
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#define IOMEM(x) ((void __force __iomem *)(x))
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#endif
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#if defined(CONFIG_ARCH_MSM7X30)
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#include "msm_iomap-7x30.h"
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#elif defined(CONFIG_ARCH_QSD8X50)
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#include "msm_iomap-8x50.h"
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#elif defined(CONFIG_ARCH_MSM8X60)
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#include "msm_iomap-8x60.h"
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#else
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#include "msm_iomap-7x00.h"
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#endif
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/* Virtual addressses shared across all MSM targets. */
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#define MSM_CSR_BASE IOMEM(0xE0001000)
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#define MSM_TMR_BASE IOMEM(0xF0200000)
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#define MSM_TMR0_BASE IOMEM(0xF0201000)
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#endif
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