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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fb4e98ab63
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Peter Korsgaard <jacmet@sunsite.dk> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Acked-by: Felipe Balbi <balbi@ti.com> Cc: Li Yang <leoli@freescale.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Wan ZongShun <mcuos.com@gmail.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
597 lines
15 KiB
C
597 lines
15 KiB
C
/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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static char *maximum_speed = "super";
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module_param(maximum_speed, charp, 0);
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MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
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/* -------------------------------------------------------------------------- */
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void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
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reg |= DWC3_GCTL_PRTCAPDIR(mode);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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/**
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* dwc3_core_soft_reset - Issues core soft reset and PHY reset
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* @dwc: pointer to our context structure
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*/
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static void dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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/* Before Resetting PHY, put Core in Reset */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg |= DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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/* Assert USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Assert USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
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mdelay(100);
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/* Clear USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Clear USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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mdelay(100);
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/* After PHYs are stable we can take Core out of reset state */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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/**
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* dwc3_free_one_event_buffer - Frees one event buffer
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* @dwc: Pointer to our controller context structure
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* @evt: Pointer to event buffer to be freed
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*/
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static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
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struct dwc3_event_buffer *evt)
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{
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dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
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}
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/**
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* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
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* @dwc: Pointer to our controller context structure
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* @length: size of the event buffer
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*
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* Returns a pointer to the allocated event buffer structure on success
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* otherwise ERR_PTR(errno).
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*/
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static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
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{
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struct dwc3_event_buffer *evt;
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evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return ERR_PTR(-ENOMEM);
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evt->dwc = dwc;
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evt->length = length;
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evt->buf = dma_alloc_coherent(dwc->dev, length,
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&evt->dma, GFP_KERNEL);
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if (!evt->buf)
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return ERR_PTR(-ENOMEM);
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return evt;
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}
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/**
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* dwc3_free_event_buffers - frees all allocated event buffers
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_free_event_buffers(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int i;
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for (i = 0; i < dwc->num_event_buffers; i++) {
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evt = dwc->ev_buffs[i];
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if (evt)
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dwc3_free_one_event_buffer(dwc, evt);
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}
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}
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/**
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* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
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* @dwc: pointer to our controller context structure
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* @length: size of event buffer
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*
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* Returns 0 on success otherwise negative errno. In the error case, dwc
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* may contain some buffers allocated but not all which were requested.
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*/
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static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
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{
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int num;
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int i;
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num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
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dwc->num_event_buffers = num;
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dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
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GFP_KERNEL);
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if (!dwc->ev_buffs) {
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dev_err(dwc->dev, "can't allocate event buffers array\n");
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return -ENOMEM;
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}
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for (i = 0; i < num; i++) {
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struct dwc3_event_buffer *evt;
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evt = dwc3_alloc_one_event_buffer(dwc, length);
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if (IS_ERR(evt)) {
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dev_err(dwc->dev, "can't allocate event buffer\n");
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return PTR_ERR(evt);
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}
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dwc->ev_buffs[i] = evt;
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}
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return 0;
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}
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/**
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* dwc3_event_buffers_setup - setup our allocated event buffers
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* @dwc: pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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static int dwc3_event_buffers_setup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < dwc->num_event_buffers; n++) {
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evt = dwc->ev_buffs[n];
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dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
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evt->buf, (unsigned long long) evt->dma,
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evt->length);
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
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lower_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
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upper_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
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evt->length & 0xffff);
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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return 0;
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}
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static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < dwc->num_event_buffers; n++) {
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evt = dwc->ev_buffs[n];
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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}
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static void dwc3_cache_hwparams(struct dwc3 *dwc)
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{
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struct dwc3_hwparams *parms = &dwc->hwparams;
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parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
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parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
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parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
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parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
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parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
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parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
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parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
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parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
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parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
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}
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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static int dwc3_core_init(struct dwc3 *dwc)
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{
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unsigned long timeout;
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u32 reg;
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int ret;
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reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
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/* This should read as U3 followed by revision number */
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if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
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dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
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ret = -ENODEV;
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goto err0;
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}
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dwc->revision = reg;
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/* issue device SoftReset too */
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timeout = jiffies + msecs_to_jiffies(500);
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dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (!(reg & DWC3_DCTL_CSFTRST))
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break;
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if (time_after(jiffies, timeout)) {
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dev_err(dwc->dev, "Reset Timed Out\n");
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ret = -ETIMEDOUT;
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goto err0;
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}
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cpu_relax();
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} while (true);
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dwc3_core_soft_reset(dwc);
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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dev_dbg(dwc->dev, "No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if (dwc->revision < DWC3_REVISION_190A)
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reg |= DWC3_GCTL_U2RSTECN;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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ret = dwc3_event_buffers_setup(dwc);
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if (ret) {
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dev_err(dwc->dev, "failed to setup event buffers\n");
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goto err0;
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}
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return 0;
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err0:
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return ret;
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}
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static void dwc3_core_exit(struct dwc3 *dwc)
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{
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dwc3_event_buffers_cleanup(dwc);
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usb_phy_shutdown(dwc->usb2_phy);
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usb_phy_shutdown(dwc->usb3_phy);
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}
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#define DWC3_ALIGN_MASK (16 - 1)
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static int dwc3_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct resource *res;
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struct dwc3 *dwc;
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struct device *dev = &pdev->dev;
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int ret = -ENOMEM;
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void __iomem *regs;
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void *mem;
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u8 mode;
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mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
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if (!mem) {
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dev_err(dev, "not enough memory\n");
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return -ENOMEM;
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}
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dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
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dwc->mem = mem;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res) {
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dev_err(dev, "missing IRQ\n");
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return -ENODEV;
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}
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dwc->xhci_resources[1].start = res->start;
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dwc->xhci_resources[1].end = res->end;
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dwc->xhci_resources[1].flags = res->flags;
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dwc->xhci_resources[1].name = res->name;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "missing memory resource\n");
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return -ENODEV;
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}
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dwc->xhci_resources[0].start = res->start;
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dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
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DWC3_XHCI_REGS_END;
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dwc->xhci_resources[0].flags = res->flags;
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dwc->xhci_resources[0].name = res->name;
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/*
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* Request memory region but exclude xHCI regs,
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* since it will be requested by the xhci-plat driver.
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*/
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res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
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resource_size(res) - DWC3_GLOBALS_REGS_START,
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dev_name(dev));
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if (!res) {
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dev_err(dev, "can't request mem region\n");
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return -ENOMEM;
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}
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regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
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if (!regs) {
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dev_err(dev, "ioremap failed\n");
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return -ENOMEM;
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}
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dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
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if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
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dev_err(dev, "no usb2 phy configured\n");
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return -EPROBE_DEFER;
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}
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dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
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if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
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dev_err(dev, "no usb3 phy configured\n");
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return -EPROBE_DEFER;
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}
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spin_lock_init(&dwc->lock);
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platform_set_drvdata(pdev, dwc);
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dwc->regs = regs;
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dwc->regs_size = resource_size(res);
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dwc->dev = dev;
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if (!strncmp("super", maximum_speed, 5))
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dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
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else if (!strncmp("high", maximum_speed, 4))
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dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
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else if (!strncmp("full", maximum_speed, 4))
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dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
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else if (!strncmp("low", maximum_speed, 3))
|
|
dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
|
|
else
|
|
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
|
|
|
|
if (of_get_property(node, "tx-fifo-resize", NULL))
|
|
dwc->needs_fifo_resize = true;
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
pm_runtime_forbid(dev);
|
|
|
|
dwc3_cache_hwparams(dwc);
|
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
ret = -ENOMEM;
|
|
goto err0;
|
|
}
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize core\n");
|
|
goto err0;
|
|
}
|
|
|
|
mode = DWC3_MODE(dwc->hwparams.hwparams0);
|
|
|
|
switch (mode) {
|
|
case DWC3_MODE_DEVICE:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
ret = dwc3_gadget_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
goto err1;
|
|
}
|
|
break;
|
|
case DWC3_MODE_HOST:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
|
|
ret = dwc3_host_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
goto err1;
|
|
}
|
|
break;
|
|
case DWC3_MODE_DRD:
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
|
|
ret = dwc3_host_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
goto err1;
|
|
}
|
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
goto err1;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(dev, "Unsupported mode of operation %d\n", mode);
|
|
goto err1;
|
|
}
|
|
dwc->mode = mode;
|
|
|
|
ret = dwc3_debugfs_init(dwc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize debugfs\n");
|
|
goto err2;
|
|
}
|
|
|
|
pm_runtime_allow(dev);
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
switch (mode) {
|
|
case DWC3_MODE_DEVICE:
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
case DWC3_MODE_HOST:
|
|
dwc3_host_exit(dwc);
|
|
break;
|
|
case DWC3_MODE_DRD:
|
|
dwc3_host_exit(dwc);
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
err1:
|
|
dwc3_core_exit(dwc);
|
|
|
|
err0:
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_remove(struct platform_device *pdev)
|
|
{
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
|
struct resource *res;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
dwc3_debugfs_exit(dwc);
|
|
|
|
switch (dwc->mode) {
|
|
case DWC3_MODE_DEVICE:
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
case DWC3_MODE_HOST:
|
|
dwc3_host_exit(dwc);
|
|
break;
|
|
case DWC3_MODE_DRD:
|
|
dwc3_host_exit(dwc);
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
dwc3_core_exit(dwc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver dwc3_driver = {
|
|
.probe = dwc3_probe,
|
|
.remove = dwc3_remove,
|
|
.driver = {
|
|
.name = "dwc3",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
MODULE_ALIAS("platform:dwc3");
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|