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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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389056e5fe
* Report 64-bit doorbells as HSA_CAP_DOORBELL_TYPE_2_0 in topology * Report cache information in topology (duplicates GFXv8 info for now) * Add device info for Vega10 support in KFD Raven is not enabled at this time as it needs additional changes in DQM to work with a single SDMA engine. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
189 lines
5.6 KiB
C
189 lines
5.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __KFD_TOPOLOGY_H__
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#define __KFD_TOPOLOGY_H__
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#include <linux/types.h>
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#include <linux/list.h>
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#include "kfd_crat.h"
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#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
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#define HSA_CAP_HOT_PLUGGABLE 0x00000001
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#define HSA_CAP_ATS_PRESENT 0x00000002
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#define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
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#define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
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#define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
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#define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
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#define HSA_CAP_VA_LIMIT 0x00000040
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#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
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#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
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#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
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#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
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#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
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#define HSA_CAP_RESERVED 0xffffc000
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#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
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#define HSA_CAP_DOORBELL_TYPE_1_0 0x1
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#define HSA_CAP_DOORBELL_TYPE_2_0 0x2
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#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
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struct kfd_node_properties {
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uint32_t cpu_cores_count;
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uint32_t simd_count;
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uint32_t mem_banks_count;
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uint32_t caches_count;
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uint32_t io_links_count;
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uint32_t cpu_core_id_base;
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uint32_t simd_id_base;
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uint32_t capability;
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uint32_t max_waves_per_simd;
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uint32_t lds_size_in_kb;
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uint32_t gds_size_in_kb;
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uint32_t wave_front_size;
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uint32_t array_count;
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uint32_t simd_arrays_per_engine;
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uint32_t cu_per_simd_array;
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uint32_t simd_per_cu;
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uint32_t max_slots_scratch_cu;
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uint32_t engine_id;
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uint32_t vendor_id;
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uint32_t device_id;
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uint32_t location_id;
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uint32_t max_engine_clk_fcompute;
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uint32_t max_engine_clk_ccompute;
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int32_t drm_render_minor;
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uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
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};
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#define HSA_MEM_HEAP_TYPE_SYSTEM 0
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#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
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#define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2
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#define HSA_MEM_HEAP_TYPE_GPU_GDS 3
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#define HSA_MEM_HEAP_TYPE_GPU_LDS 4
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#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5
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#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
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#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
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#define HSA_MEM_FLAGS_RESERVED 0xfffffffc
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struct kfd_mem_properties {
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struct list_head list;
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uint32_t heap_type;
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uint64_t size_in_bytes;
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uint32_t flags;
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uint32_t width;
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uint32_t mem_clk_max;
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struct kobject *kobj;
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struct attribute attr;
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};
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#define HSA_CACHE_TYPE_DATA 0x00000001
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#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
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#define HSA_CACHE_TYPE_CPU 0x00000004
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#define HSA_CACHE_TYPE_HSACU 0x00000008
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#define HSA_CACHE_TYPE_RESERVED 0xfffffff0
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struct kfd_cache_properties {
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struct list_head list;
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uint32_t processor_id_low;
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uint32_t cache_level;
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uint32_t cache_size;
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uint32_t cacheline_size;
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uint32_t cachelines_per_tag;
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uint32_t cache_assoc;
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uint32_t cache_latency;
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uint32_t cache_type;
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uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
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struct kobject *kobj;
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struct attribute attr;
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};
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struct kfd_iolink_properties {
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struct list_head list;
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uint32_t iolink_type;
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uint32_t ver_maj;
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uint32_t ver_min;
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uint32_t node_from;
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uint32_t node_to;
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uint32_t weight;
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uint32_t min_latency;
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uint32_t max_latency;
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uint32_t min_bandwidth;
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uint32_t max_bandwidth;
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uint32_t rec_transfer_size;
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uint32_t flags;
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struct kobject *kobj;
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struct attribute attr;
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};
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struct kfd_perf_properties {
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struct list_head list;
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char block_name[16];
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uint32_t max_concurrent;
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struct attribute_group *attr_group;
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};
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struct kfd_topology_device {
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struct list_head list;
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uint32_t gpu_id;
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uint32_t proximity_domain;
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struct kfd_node_properties node_props;
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struct list_head mem_props;
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uint32_t cache_count;
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struct list_head cache_props;
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uint32_t io_link_count;
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struct list_head io_link_props;
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struct list_head perf_props;
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struct kfd_dev *gpu;
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struct kobject *kobj_node;
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struct kobject *kobj_mem;
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struct kobject *kobj_cache;
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struct kobject *kobj_iolink;
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struct kobject *kobj_perf;
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struct attribute attr_gpuid;
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struct attribute attr_name;
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struct attribute attr_props;
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uint8_t oem_id[CRAT_OEMID_LENGTH];
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uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
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uint32_t oem_revision;
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};
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struct kfd_system_properties {
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uint32_t num_devices; /* Number of H-NUMA nodes */
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uint32_t generation_count;
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uint64_t platform_oem;
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uint64_t platform_id;
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uint64_t platform_rev;
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struct kobject *kobj_topology;
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struct kobject *kobj_nodes;
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struct attribute attr_genid;
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struct attribute attr_props;
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};
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struct kfd_topology_device *kfd_create_topology_device(
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struct list_head *device_list);
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void kfd_release_topology_device_list(struct list_head *device_list);
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#endif /* __KFD_TOPOLOGY_H__ */
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