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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d06fa5a118
Pull in generic CPU topology changes from Paul Walmsley (RISC-V). * tag 'common/for-v5.4-rc1/cpu-topology' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: MAINTAINERS: Add an entry for generic architecture topology base: arch_topology: update Kconfig help description RISC-V: Parse cpu topology during boot. arm: Use common cpu_topology structure and functions. cpu-topology: Move cpu topology code to common code. dt-binding: cpu-topology: Move cpu-map to a common binding. Documentation: DT: arm: add support for sockets defining package boundaries
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* arch/arm64/kernel/topology.c
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*
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* Copyright (C) 2011,2013,2014 Linaro Limited.
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*
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* Based on the arm32 version written by Vincent Guittot in turn based on
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* arch/sh/kernel/topology.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/acpi.h>
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#include <linux/arch_topology.h>
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#include <linux/cacheinfo.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/topology.h>
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void store_cpu_topology(unsigned int cpuid)
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{
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struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
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u64 mpidr;
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if (cpuid_topo->package_id != -1)
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goto topology_populated;
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mpidr = read_cpuid_mpidr();
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/* Uniprocessor systems can rely on default topology values */
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if (mpidr & MPIDR_UP_BITMASK)
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return;
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/* Create cpu topology mapping based on MPIDR. */
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if (mpidr & MPIDR_MT_BITMASK) {
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/* Multiprocessor system : Multi-threads per core */
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cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) |
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MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8;
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} else {
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/* Multiprocessor system : Single-thread per core */
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) |
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MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 |
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MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16;
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}
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pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
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cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
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cpuid_topo->thread_id, mpidr);
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topology_populated:
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update_siblings_masks(cpuid);
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}
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#ifdef CONFIG_ACPI
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static bool __init acpi_cpu_is_threaded(int cpu)
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{
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int is_threaded = acpi_pptt_cpu_is_thread(cpu);
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/*
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* if the PPTT doesn't have thread information, assume a homogeneous
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* machine and return the current CPU's thread state.
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*/
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if (is_threaded < 0)
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is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK;
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return !!is_threaded;
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}
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/*
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* Propagate the topology information of the processor_topology_node tree to the
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* cpu_topology array.
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*/
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int __init parse_acpi_topology(void)
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{
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int cpu, topology_id;
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if (acpi_disabled)
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return 0;
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for_each_possible_cpu(cpu) {
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int i, cache_id;
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topology_id = find_acpi_cpu_topology(cpu, 0);
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if (topology_id < 0)
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return topology_id;
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if (acpi_cpu_is_threaded(cpu)) {
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cpu_topology[cpu].thread_id = topology_id;
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topology_id = find_acpi_cpu_topology(cpu, 1);
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cpu_topology[cpu].core_id = topology_id;
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} else {
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cpu_topology[cpu].thread_id = -1;
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cpu_topology[cpu].core_id = topology_id;
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}
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topology_id = find_acpi_cpu_topology_package(cpu);
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cpu_topology[cpu].package_id = topology_id;
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i = acpi_find_last_cache_level(cpu);
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if (i > 0) {
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/*
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* this is the only part of cpu_topology that has
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* a direct relationship with the cache topology
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*/
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cache_id = find_acpi_cpu_cache_topology(cpu, i);
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if (cache_id > 0)
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cpu_topology[cpu].llc_id = cache_id;
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}
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}
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return 0;
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}
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#endif
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