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cccf34e941
MT_SMP is not the only SMP option for MT cores. The MT_SMP option allows more than one VPE per core to appear as a secondary CPU in the system. Because of how CM works, it propagates the address-based cache ops to the secondary cores but not the index-based ones. Because of that, the code does not use IPIs to flush the L1 caches on secondary cores because the CM would have done that already. However, the CM functionality is independent of the type of SMP kernel so even in non-MT kernels, IPIs are not necessary. As a result of which, we change the conditional to depend on the CM presence. Moreover, since VPEs on the same core share the same L1 caches, there is no need to send an IPI on all of them so we calculate a suitable cpumask with only one VPE per core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10654/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*
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* Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
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* Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2002 Ralf Baechle
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* Copyright (C) 2000, 2001 Broadcom Corporation
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*/
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#ifndef __ASM_SMP_H
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#define __ASM_SMP_H
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#include <linux/bitops.h>
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#include <linux/linkage.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/atomic.h>
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#include <asm/smp-ops.h>
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extern int smp_num_siblings;
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extern cpumask_t cpu_sibling_map[];
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extern cpumask_t cpu_core_map[];
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extern cpumask_t cpu_foreign_map;
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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/* Map from cpu id to sequential logical cpu number. This will only
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not be idempotent when cpus failed to come on-line. */
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extern int __cpu_number_map[NR_CPUS];
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#define cpu_number_map(cpu) __cpu_number_map[cpu]
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/* The reverse map from sequential logical cpu number to cpu id. */
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extern int __cpu_logical_map[NR_CPUS];
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#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
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#define NO_PROC_ID (-1)
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#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
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#define SMP_CALL_FUNCTION 0x2
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/* Octeon - Tell another core to flush its icache */
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#define SMP_ICACHE_FLUSH 0x4
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/* Used by kexec crashdump to save all cpu's state */
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#define SMP_DUMP 0x8
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#define SMP_ASK_C0COUNT 0x10
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extern cpumask_t cpu_callin_map;
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/* Mask of CPUs which are currently definitely operating coherently */
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extern cpumask_t cpu_coherent_mask;
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extern void asmlinkage smp_bootstrap(void);
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/*
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* this function sends a 'reschedule' IPI to another CPU.
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* it goes straight through and wastes no time serializing
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* anything. Worst case is that we lose a reschedule ...
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*/
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static inline void smp_send_reschedule(int cpu)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static inline int __cpu_disable(void)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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return mp_ops->cpu_disable();
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}
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static inline void __cpu_die(unsigned int cpu)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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mp_ops->cpu_die(cpu);
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}
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extern void play_dead(void);
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#endif
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extern asmlinkage void smp_call_function_interrupt(void);
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static inline void arch_send_call_function_single_ipi(int cpu)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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mp_ops->send_ipi_mask(cpumask_of(cpu), SMP_CALL_FUNCTION);
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}
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static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
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}
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#if defined(CONFIG_KEXEC)
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extern void (*dump_ipi_function_ptr)(void *);
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void dump_send_ipi(void (*dump_ipi_callback)(void *));
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#endif
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#endif /* __ASM_SMP_H */
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