linux_dsm_epyc7002/virt/kvm/arm
Christoffer Dall 8bf9a701e1 arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs
The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only.
We currently simulate this behavior by writing a hardcoded value to the
register for the SGIs and PPIs on every write of these bits to the
register (ignoring what the guest actually wrote), and by writing the
same value as the reset value to the register.

This is a bit counter-intuitive, as the register is RO for these bits,
and we can just implement it that way, allowing us to control the value
of the bits purely in the reset code.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2015-10-22 23:01:42 +02:00
..
arch_timer.c arm/arm64: KVM: arch_timer: Only schedule soft timer on vcpu_block 2015-10-22 23:01:42 +02:00
vgic-v2-emul.c KVM: arm/arm64: rework MMIO abort handling to use KVM MMIO bus 2015-03-30 17:07:19 +01:00
vgic-v2.c KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR 2015-08-12 11:28:24 +01:00
vgic-v3-emul.c KVM: arm: vgic: Drop useless Group0 warning 2015-06-17 09:58:12 +01:00
vgic-v3.c arm/arm64: KVM: Remove 'config KVM_ARM_MAX_VCPUS' 2015-09-17 13:13:27 +01:00
vgic.c arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs 2015-10-22 23:01:42 +02:00
vgic.h KVM: arm/arm64: rework MMIO abort handling to use KVM MMIO bus 2015-03-30 17:07:19 +01:00