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48df28b859
This patch removes the parent clock 'ethif' in bindings, since we don't need to control the parent of a clock in current clock framework. Moreover, the clocks are get by name in the driver, thus this change does not break backwards compatibility. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
26 lines
879 B
Plaintext
26 lines
879 B
Plaintext
MediaTek cryptographic accelerators
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Required properties:
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- compatible: Should be "mediatek,eip97-crypto"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the five crypto engines interrupts in numeric
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order. These are global system and four descriptor rings.
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- clocks: the clock used by the core
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- clock-names: Must contain "cryp".
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- power-domains: Must contain a reference to the PM domain.
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Example:
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crypto: crypto@1b240000 {
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compatible = "mediatek,eip97-crypto";
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reg = <0 0x1b240000 0 0x20000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
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clocks = <ðsys CLK_ETHSYS_CRYPTO>;
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clock-names = "cryp";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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};
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