mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 07:16:40 +07:00
8d1cf34e7a
This patch tweaks the way some PTE bit combinations are defined, in such a way that the 32 and 64-bit variant become almost identical and that will make it easier to bring in a new common pte-* file for the new variant of the Book3-E support. The combination of bits defining access to kernel pages are now clearly separated from the combination used by userspace and the core VM. The resulting generated code should remain identical unless I made a mistake. Note: While at it, I removed a non-sensical statement related to CONFIG_KGDB in ppc_mmu_32.c which could cause kernel mappings to be user accessible when that option is enabled. Probably something that bitrot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
348 lines
8.5 KiB
C
348 lines
8.5 KiB
C
/*
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* Common CPM code
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* Some parts derived from commproc.c/cpm2_common.c, which is:
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* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
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* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2006 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <asm/udbg.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/rheap.h>
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#include <asm/cpm.h>
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#include <mm/mmu_decl.h>
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
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#include <linux/of_gpio.h>
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#endif
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#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
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static u32 __iomem *cpm_udbg_txdesc =
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(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
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static void udbg_putc_cpm(char c)
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{
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u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
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if (c == '\n')
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udbg_putc_cpm('\r');
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while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
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;
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out_8(txbuf, c);
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out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
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}
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void __init udbg_init_cpm(void)
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{
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if (cpm_udbg_txdesc) {
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#ifdef CONFIG_CPM2
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setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
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#endif
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udbg_putc = udbg_putc_cpm;
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}
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}
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#endif
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static spinlock_t cpm_muram_lock;
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static rh_block_t cpm_boot_muram_rh_block[16];
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static rh_info_t cpm_muram_info;
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static u8 __iomem *muram_vbase;
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static phys_addr_t muram_pbase;
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/* Max address size we deal with */
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#define OF_MAX_ADDR_CELLS 4
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int __init cpm_muram_init(void)
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{
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struct device_node *np;
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struct resource r;
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u32 zero[OF_MAX_ADDR_CELLS] = {};
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resource_size_t max = 0;
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int i = 0;
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int ret = 0;
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spin_lock_init(&cpm_muram_lock);
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/* initialize the info header */
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rh_init(&cpm_muram_info, 1,
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sizeof(cpm_boot_muram_rh_block) /
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sizeof(cpm_boot_muram_rh_block[0]),
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cpm_boot_muram_rh_block);
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
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if (!np) {
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/* try legacy bindings */
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np = of_find_node_by_name(NULL, "data-only");
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if (!np) {
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printk(KERN_ERR "Cannot find CPM muram data node");
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ret = -ENODEV;
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goto out;
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}
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}
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muram_pbase = of_translate_address(np, zero);
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if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
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printk(KERN_ERR "Cannot translate zero through CPM muram node");
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ret = -ENODEV;
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goto out;
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}
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while (of_address_to_resource(np, i++, &r) == 0) {
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if (r.end > max)
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max = r.end;
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rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
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r.end - r.start + 1);
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}
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muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
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if (!muram_vbase) {
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printk(KERN_ERR "Cannot map CPM muram");
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ret = -ENOMEM;
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}
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out:
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of_node_put(np);
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return ret;
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}
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/**
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* cpm_muram_alloc - allocate the requested size worth of multi-user ram
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* @size: number of bytes to allocate
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* @align: requested alignment, in bytes
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*
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* This function returns an offset into the muram area.
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* Use cpm_dpram_addr() to get the virtual address of the area.
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* Use cpm_muram_free() to free the allocation.
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*/
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unsigned long cpm_muram_alloc(unsigned long size, unsigned long align)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_muram_lock, flags);
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cpm_muram_info.alignment = align;
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start = rh_alloc(&cpm_muram_info, size, "commproc");
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spin_unlock_irqrestore(&cpm_muram_lock, flags);
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return start;
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}
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EXPORT_SYMBOL(cpm_muram_alloc);
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/**
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* cpm_muram_free - free a chunk of multi-user ram
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* @offset: The beginning of the chunk as returned by cpm_muram_alloc().
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*/
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int cpm_muram_free(unsigned long offset)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&cpm_muram_lock, flags);
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ret = rh_free(&cpm_muram_info, offset);
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spin_unlock_irqrestore(&cpm_muram_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_muram_free);
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/**
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* cpm_muram_alloc_fixed - reserve a specific region of multi-user ram
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* @offset: the offset into the muram area to reserve
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* @size: the number of bytes to reserve
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*
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* This function returns "start" on success, -ENOMEM on failure.
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* Use cpm_dpram_addr() to get the virtual address of the area.
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* Use cpm_muram_free() to free the allocation.
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*/
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unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_muram_lock, flags);
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cpm_muram_info.alignment = 1;
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start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
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spin_unlock_irqrestore(&cpm_muram_lock, flags);
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return start;
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}
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EXPORT_SYMBOL(cpm_muram_alloc_fixed);
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/**
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* cpm_muram_addr - turn a muram offset into a virtual address
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* @offset: muram offset to convert
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*/
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void __iomem *cpm_muram_addr(unsigned long offset)
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{
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return muram_vbase + offset;
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}
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EXPORT_SYMBOL(cpm_muram_addr);
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unsigned long cpm_muram_offset(void __iomem *addr)
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{
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return addr - (void __iomem *)muram_vbase;
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}
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EXPORT_SYMBOL(cpm_muram_offset);
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/**
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* cpm_muram_dma - turn a muram virtual address into a DMA address
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* @offset: virtual address from cpm_muram_addr() to convert
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*/
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dma_addr_t cpm_muram_dma(void __iomem *addr)
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{
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return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
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}
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EXPORT_SYMBOL(cpm_muram_dma);
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
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struct cpm2_ioports {
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u32 dir, par, sor, odr, dat;
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u32 res[3];
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};
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struct cpm2_gpio32_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/* shadowed data register to clear/set bits safely */
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u32 cpdata;
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};
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static inline struct cpm2_gpio32_chip *
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to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
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{
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return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
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}
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static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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cpm2_gc->cpdata = in_be32(&iop->dat);
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}
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static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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u32 pin_mask;
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pin_mask = 1 << (31 - gpio);
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return !!(in_be32(&iop->dat) & pin_mask);
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}
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static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
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int value)
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{
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struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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if (value)
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cpm2_gc->cpdata |= pin_mask;
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else
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cpm2_gc->cpdata &= ~pin_mask;
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out_be32(&iop->dat, cpm2_gc->cpdata);
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}
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static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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__cpm2_gpio32_set(mm_gc, pin_mask, value);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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}
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static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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setbits32(&iop->dir, pin_mask);
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__cpm2_gpio32_set(mm_gc, pin_mask, val);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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return 0;
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}
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static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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clrbits32(&iop->dir, pin_mask);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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return 0;
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}
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int cpm2_gpiochip_add32(struct device_node *np)
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{
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struct cpm2_gpio32_chip *cpm2_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct of_gpio_chip *of_gc;
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struct gpio_chip *gc;
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cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
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if (!cpm2_gc)
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return -ENOMEM;
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spin_lock_init(&cpm2_gc->lock);
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mm_gc = &cpm2_gc->mm_gc;
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of_gc = &mm_gc->of_gc;
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gc = &of_gc->gc;
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mm_gc->save_regs = cpm2_gpio32_save_regs;
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of_gc->gpio_cells = 2;
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gc->ngpio = 32;
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gc->direction_input = cpm2_gpio32_dir_in;
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gc->direction_output = cpm2_gpio32_dir_out;
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gc->get = cpm2_gpio32_get;
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gc->set = cpm2_gpio32_set;
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return of_mm_gpiochip_add(np, mm_gc);
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}
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#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
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