mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 01:29:13 +07:00
ed3a03b707
This activates the AFS partition parsing on the RealView family. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
469 lines
11 KiB
Plaintext
469 lines
11 KiB
Plaintext
/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-eb";
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chosen { };
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c;
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};
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memory {
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device_type = "memory";
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/* 128 MiB memory @ 0x0 */
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reg = <0x00000000 0x08000000>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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mclk: mclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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kmiclk: kmiclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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wdogclk: wdogclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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flash0@40000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x40000000 0x04000000>;
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bank-width = <4>;
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partitions {
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compatible = "arm,arm-firmware-suite";
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};
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};
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flash1@44000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x44000000 0x04000000>;
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bank-width = <4>;
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partitions {
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compatible = "arm,arm-firmware-suite";
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};
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};
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/* SMSC LAN91C111 ethernet with PHY and EEPROM */
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ethernet: ethernet@4e000000 {
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compatible = "smsc,lan91c111";
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reg = <0x4e000000 0x10000>;
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/*
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* This means the adapter can be accessed with 8, 16 or
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* 32 bit reads/writes.
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*/
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reg-io-width = <7>;
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};
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usb: usb@4f000000 {
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compatible = "nxp,usb-isp1761";
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reg = <0x4f000000 0x20000>;
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port1-otg;
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};
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bridge {
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compatible = "ti,ths8134a", "ti,ths8134";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_con_in: endpoint {
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remote-endpoint = <&vga_bridge_out>;
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};
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};
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};
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/* These peripherals are inside the FPGA */
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fpga {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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oscclk0: osc0@0c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x0C>;
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clocks = <&xtal24mhz>;
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};
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oscclk1: osc1@10 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x10>;
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clocks = <&xtal24mhz>;
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};
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oscclk2: osc2@14 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x14>;
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clocks = <&xtal24mhz>;
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};
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oscclk3: osc3@18 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x18>;
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clocks = <&xtal24mhz>;
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};
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oscclk4: osc4@1c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x1c>;
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clocks = <&xtal24mhz>;
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};
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};
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i2c: i2c@10002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,versatile-i2c";
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reg = <0x10002000 0x1000>;
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rtc@68 {
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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};
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aaci: aaci@10004000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x10004000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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mmc: mmcsd@10005000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x10005000 0x1000>;
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/* Due to frequent FIFO overruns, use just 500 kHz */
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max-frequency = <500000>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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clocks = <&mclk>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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vmmc-supply = <&vmmc>;
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cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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};
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kmi0: kmi@10006000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x10006000 0x1000>;
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi1: kmi@10007000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x10007000 0x1000>;
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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charlcd: fpga_charlcd: charlcd@10008000 {
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compatible = "arm,versatile-lcd";
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reg = <0x10008000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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serial0: serial@10009000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x10009000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial1: serial@1000a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000a000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial2: serial@1000b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000b000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial3: serial@1000c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000c000 0x1000>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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ssp: spi@1000d000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1000d000 0x1000>;
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clocks = <&sspclk>, <&pclk>;
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clock-names = "SSPCLK", "apb_pclk";
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};
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wdog: watchdog@10010000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x10010000 0x1000>;
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clocks = <&wdogclk>, <&pclk>;
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clock-names = "wdogclk", "apb_pclk";
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status = "disabled";
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};
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timer01: timer@10011000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10011000 0x1000>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer23: timer@10012000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10012000 0x1000>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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gpio0: gpio@10013000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10013000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@10014000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10014000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpio2: gpio@10015000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10015000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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rtc: rtc@10017000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x10017000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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clcd: clcd@10020000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x10020000 0x1000>;
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interrupt-names = "combined";
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clocks = <&oscclk0>, <&pclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 1024x768 16bpp @65MHz works fine */
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max-memory-bandwidth = <95000000>;
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port {
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clcd_pads: endpoint {
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remote-endpoint = <&vga_bridge_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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};
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};
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