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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a6cbcdd5ab
The CPPC registers can also be accessed via functional fixed hardware addresse(FFH) in X86. Add support by modifying cpc_read and cpc_write to be able to read/write MSRs on x86 platform on per cpu basis. Also with this change, acpi_cppc_processor_probe doesn't bail out if address space id is not equal to PCC or memory address space and FFH is supported on the system. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* cppc_msr.c: MSR Interface for CPPC
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* Copyright (c) 2016, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <acpi/cppc_acpi.h>
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#include <asm/msr.h>
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/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
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bool cpc_ffh_supported(void)
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{
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return true;
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}
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int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
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{
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int err;
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, val);
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if (!err) {
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u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
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reg->bit_offset);
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*val &= mask;
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*val >>= reg->bit_offset;
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}
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return err;
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}
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int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
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{
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u64 rd_val;
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int err;
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val);
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if (!err) {
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u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
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reg->bit_offset);
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val <<= reg->bit_offset;
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val &= mask;
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rd_val &= ~mask;
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rd_val |= val;
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err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val);
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}
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return err;
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}
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