mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8baebe3064
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJUBiq/AAoJEPOmecmc0R2BE5EH/0tpqDdvMkIWFeT4Wv7lqbds CFzg6kP7T14tzRgEAQlO2EeZ4SvsWhBRrXo1GKy7GcsTuouRikpADF3HC3v3hPgw x1Gi/t0ZpqHZEymV/jUJx7Cakqhz65tUK4SrDqGIc20m2XrBHIQD1vg7yKJpzVcX nVtmuhAicyxGYUNYT3t3XXToWBWXhUQ0rBDymAfP3eUbzKfFMBi47C0klqE8/DZQ bdEjRSTTrlmznSL9AVqXAlfZ+DwCTS4qO+4nZ2LTYnZjTEqxbU2lGKwe5z+0f/sg /XdWhtk9YgJAYE4WDMNpQkcrYU/cXOD+EWCrvv1+SGA1YOJnUgRlkFwlhWO0uTM= =SrWP -----END PGP SIGNATURE----- Merge tag 'v3.18-rockchip-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "rockchip dma support" from Heiko Stuebner: Enable the AMBA bus and add necessary dma-controller dts nodes * tag 'v3.18-rockchip-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add rk3066 and rk3188 dma controllers ARM: dts: rockchip: add rk3288 dma controllers ARM: rockchip: enable the AMBA bus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
732 lines
17 KiB
Plaintext
732 lines
17 KiB
Plaintext
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3288";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x500>;
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};
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cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x501>;
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};
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cpu@502 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x502>;
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};
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cpu@503 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x503>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff250000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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dmac_bus_ns: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff600000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dmac_bus_s: dma-controller@ffb20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffb20000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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sdmmc: dwmmc@ff0c0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0c0000 0x4000>;
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status = "disabled";
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};
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emmc: dwmmc@ff0f0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0f0000 0x4000>;
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status = "disabled";
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};
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saradc: saradc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0xff100000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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i2c1: i2c@ff140000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff140000 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff150000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff150000 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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i2c4: i2c@ff160000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff160000 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C4>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff170000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C5>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff180000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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status = "disabled";
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};
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uart1: serial@ff190000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff190000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart2: serial@ff690000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff690000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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status = "disabled";
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};
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uart3: serial@ff1b0000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff1b0000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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};
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uart4: serial@ff1c0000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff1c0000 0x100>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_xfer>;
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status = "disabled";
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};
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usb_host0_ehci: usb@ff500000 {
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compatible = "generic-ehci";
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reg = <0xff500000 0x100>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_USBHOST0>;
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clock-names = "usbhost";
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status = "disabled";
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};
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/* NOTE: ohci@ff520000 doesn't actually work on hardware */
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usb_hsic: usb@ff5c0000 {
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compatible = "generic-ehci";
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reg = <0xff5c0000 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HSIC>;
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clock-names = "usbhost";
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status = "disabled";
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff650000 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c2: i2c@ff660000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff660000 0x1000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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pwm0: pwm@ff680000 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0xff680000 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm1: pwm@ff680010 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0xff680010 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm2: pwm@ff680020 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0xff680020 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm3: pwm@ff680030 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0xff680030 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pmu: power-management@ff730000 {
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compatible = "rockchip,rk3288-pmu", "syscon";
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reg = <0xff730000 0x100>;
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};
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sgrf: syscon@ff740000 {
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compatible = "rockchip,rk3288-sgrf", "syscon";
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reg = <0xff740000 0x1000>;
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};
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cru: clock-controller@ff760000 {
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compatible = "rockchip,rk3288-cru";
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reg = <0xff760000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3288-grf", "syscon";
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reg = <0xff770000 0x1000>;
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};
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wdt: watchdog@ff800000 {
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compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
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reg = <0xff800000 0x100>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0xffc01000 0x1000>,
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<0xffc02000 0x1000>,
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<0xffc04000 0x2000>,
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<0xffc06000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3288-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@ff750000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff750000 0x100>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@ff780000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff780000 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@ff790000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff790000 0x100>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@ff7a0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7a0000 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio4@ff7b0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7b0000 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio5@ff7c0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7c0000 0x100>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO5>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio6@ff7d0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7d0000 0x100>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio7@ff7e0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7e0000 0x100>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO7>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio8: gpio8@ff7f0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7f0000 0x100>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO8>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 16 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<8 5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<7 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<7 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_cd: sdmcc-cd {
|
|
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 17 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 18 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 19 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_pwr: emmc-pwr {
|
|
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 3 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 3 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 4 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 5 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 6 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 7 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
|
|
<5 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
|
|
<7 23 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
|
|
<7 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins = <5 12 3 &pcfg_pull_up>,
|
|
<5 13 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_cts: uart4-cts {
|
|
rockchip,pins = <5 14 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_rts: uart4-rts {
|
|
rockchip,pins = <5 15 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <7 22 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <7 23 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|